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flat assembler > Non-x86 architectures > FASMARM v1.43 - Cross assembler for ARM CPUs

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bzt



Joined: 09 Nov 2018
Posts: 41
revolution wrote:
Are there any programming IDEs for Android?
Yeah sure, it's called vi Smile

revolution wrote:
It wouldn't be a very good platform for code development.
Some of the tablets with a BT keyboard could be useable at some degree. Wouldn't be my first choice though, I give you that.

On @hyphz's question, qemu supports both
"-M raspi2 -kernel kernel7.img" (for AArch32)
"-M raspi3 -kernel kernel8.img" (for AArch64)
these days. The "-cpu" and other arguments no longer needed, and framebuffer works too (at least VC is emulated at mailbox level, not sure about GL; video and image decoding definitely missing, as well as many BCM peripherals).

Cheers,
bzt
Post 22 Dec 2018, 19:12
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 16651
Location: In your JS exploiting you and your system
There are currently no plans to rewrite fasmarm in native ARM code.

So to run fasmarm, or fasm for that matter, on a tablet or phone you will need an 80386 emulator/VM. To run the IDE you will also need a windows VM or have WINE running also.
Post 23 Dec 2018, 17:13
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guignol



Joined: 06 Dec 2008
Posts: 554
and no muscle, i get it

_________________
qiq;
Post 29 Dec 2018, 13:46
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TmEE



Joined: 19 Jun 2019
Posts: 2
Location: Estonia
Allo !

I have been using FASMARM for STM32 development for a little while and I have found a bug regarding immediate offset handling.

FASMARM allows the more conventional syntax of [Rx+123] instead of [Rx,123] that is standard in ARM and I have been using it instead but I have found out that if you use the offset in hexadecimal (using $) the instruction will not always assemble with correct offset.
LDR R0, [R8+$12] produced offset equivalent of $18 in some tests I was performing.
LDR R0, [R8,$12] gives correct result.

I have converted all my code to use the conventional ARM syntax but it would be nice if this could be looked at and perhaps fixed or maybe opposite and disallowed entirely. I cannot say I'm a big fan of the ARM syntax, especially with 68K background where similar operations use more intuitive representation.
Post 19 Jun 2019, 22:33
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 16651
Location: In your JS exploiting you and your system
Yes, you are right. And it appears to only affect thumb mode long form instructions using high registers.
Code:
ldr     r0,[r8+$12]
thumb
ldr     r0,[r8+$12]
ldr     r0,[r0+$12]
ldr     r0,[r0+$10]    
Output:
Code:
00000000: E5980012 V1     ldr   r0,[r8,0x12]
thumb
00000008: F8D8001A 7M     ldr   r0,[r8,0x1A] ;Oops
0000000C: F8D00012 7M     ldr   r0,[r0,0x12]
00000010:     6900 V4T    ldr   r0,[r0,0x10]    
It is still another week before I will be back to my dev system. I'll update fasmarm with a fix then.
Post 19 Jun 2019, 22:54
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guignol



Joined: 06 Dec 2008
Posts: 554
revolution wrote:
And it appears to only affect thumb mode long form instructions using high registers.
can you actually pronounce that quick
Post 20 Jun 2019, 03:12
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TmEE



Joined: 19 Jun 2019
Posts: 2
Location: Estonia
Thänk you for the quick look at the matter, I look forward to any developments ~

EDIT: I am wondering if there's a better way to define interrupt vectors (or other addresses) than to do DW Label+1 ? Lowest bit needs to be set as I found out or the CPU will hard fault. Perhaps there could be dedicated data definition like say DV (define vector) which automatically sets the lowest bit ?
Post 20 Jun 2019, 12:49
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