Yeah sure, it's called vi

Some of the tablets with a BT keyboard could be useable at some degree. Wouldn't be my first choice though, I give you that.

On @hyphz's question, qemu supports both
"-M raspi2 -kernel kernel7.img" (for AArch32)
"-M raspi3 -kernel kernel8.img" (for AArch64)
these days. The "-cpu" and other arguments no longer needed, and framebuffer works too (at least VC is emulated at mailbox level, not sure about GL; video and image decoding definitely missing, as well as many BCM peripherals).

Cheers,
bzt

There are currently no plans to rewrite fasmarm in native ARM code.

So to run fasmarm, or fasm for that matter, on a tablet or phone you will need an 80386 emulator/VM. To run the IDE you will also need a windows VM or have WINE running also.

and no muscle, i get it

Allo !

I have been using FASMARM for STM32 development for a little while and I have found a bug regarding immediate offset handling.

FASMARM allows the more conventional syntax of [Rx+123] instead of [Rx,123] that is standard in ARM and I have been using it instead but I have found out that if you use the offset in hexadecimal (using $) the instruction will not always assemble with correct offset.
LDR R0, [R8+$12] produced offset equivalent of $18 in some tests I was performing.
LDR R0, [R8,$12] gives correct result.

I have converted all my code to use the conventional ARM syntax but it would be nice if this could be looked at and perhaps fixed or maybe opposite and disallowed entirely. I cannot say I'm a big fan of the ARM syntax, especially with 68K background where similar operations use more intuitive representation.

Yes, you are right. And it appears to only affect thumb mode long form instructions using high registers. Output: It is still another week before I will be back to my dev system. I'll update fasmarm with a fix then.

can you actually pronounce that quick

Thänk you for the quick look at the matter, I look forward to any developments ~

EDIT: I am wondering if there's a better way to define interrupt vectors (or other addresses) than to do DW Label+1 ? Lowest bit needs to be set as I found out or the CPU will hard fault. Perhaps there could be dedicated data definition like say DV (define vector) which automatically sets the lowest bit ?

Looks like this has fallen into cracks lol (I'm not in actual hurry, I only now remembered to check up on this)

Yeah, I thought some time back that it would be a week till I got back to my dev system. But the 737MAX thing has turned into a really big problem. I should refrain from predicting an end time. As it looks now it might be never. Sigh.

For your suggestion of DV (which I only saw now). You can use a macro to do the CPU specific requirements. It isn't part of the instruction set so I think making special assembler directives isn't the proper place to have it.