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Index > Non-x86 architectures > FASMARM v1.43 - Cross assembler for ARM CPUs

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bzt



Joined: 09 Nov 2018
Posts: 43
bzt
revolution wrote:
Are there any programming IDEs for Android?
Yeah sure, it's called vi Smile

revolution wrote:
It wouldn't be a very good platform for code development.
Some of the tablets with a BT keyboard could be useable at some degree. Wouldn't be my first choice though, I give you that.

On @hyphz's question, qemu supports both
"-M raspi2 -kernel kernel7.img" (for AArch32)
"-M raspi3 -kernel kernel8.img" (for AArch64)
these days. The "-cpu" and other arguments no longer needed, and framebuffer works too (at least VC is emulated at mailbox level, not sure about GL; video and image decoding definitely missing, as well as many BCM peripherals).

Cheers,
bzt
Post 22 Dec 2018, 19:12
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 16850
Location: In your JS exploiting you and your system
revolution
There are currently no plans to rewrite fasmarm in native ARM code.

So to run fasmarm, or fasm for that matter, on a tablet or phone you will need an 80386 emulator/VM. To run the IDE you will also need a windows VM or have WINE running also.
Post 23 Dec 2018, 17:13
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guignol



Joined: 06 Dec 2008
Posts: 631
guignol
and no muscle, i get it

_________________
qiq;
Post 29 Dec 2018, 13:46
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TmEE



Joined: 19 Jun 2019
Posts: 3
Location: Estonia
TmEE
Allo !

I have been using FASMARM for STM32 development for a little while and I have found a bug regarding immediate offset handling.

FASMARM allows the more conventional syntax of [Rx+123] instead of [Rx,123] that is standard in ARM and I have been using it instead but I have found out that if you use the offset in hexadecimal (using $) the instruction will not always assemble with correct offset.
LDR R0, [R8+$12] produced offset equivalent of $18 in some tests I was performing.
LDR R0, [R8,$12] gives correct result.

I have converted all my code to use the conventional ARM syntax but it would be nice if this could be looked at and perhaps fixed or maybe opposite and disallowed entirely. I cannot say I'm a big fan of the ARM syntax, especially with 68K background where similar operations use more intuitive representation.
Post 19 Jun 2019, 22:33
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 16850
Location: In your JS exploiting you and your system
revolution
Yes, you are right. And it appears to only affect thumb mode long form instructions using high registers.
Code:
ldr     r0,[r8+$12]
thumb
ldr     r0,[r8+$12]
ldr     r0,[r0+$12]
ldr     r0,[r0+$10]    
Output:
Code:
00000000: E5980012 V1     ldr   r0,[r8,0x12]
thumb
00000008: F8D8001A 7M     ldr   r0,[r8,0x1A] ;Oops
0000000C: F8D00012 7M     ldr   r0,[r0,0x12]
00000010:     6900 V4T    ldr   r0,[r0,0x10]    
It is still another week before I will be back to my dev system. I'll update fasmarm with a fix then.
Post 19 Jun 2019, 22:54
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guignol



Joined: 06 Dec 2008
Posts: 631
guignol
revolution wrote:
And it appears to only affect thumb mode long form instructions using high registers.
can you actually pronounce that quick
Post 20 Jun 2019, 03:12
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TmEE



Joined: 19 Jun 2019
Posts: 3
Location: Estonia
TmEE
Thänk you for the quick look at the matter, I look forward to any developments ~

EDIT: I am wondering if there's a better way to define interrupt vectors (or other addresses) than to do DW Label+1 ? Lowest bit needs to be set as I found out or the CPU will hard fault. Perhaps there could be dedicated data definition like say DV (define vector) which automatically sets the lowest bit ?
Post 20 Jun 2019, 12:49
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TmEE



Joined: 19 Jun 2019
Posts: 3
Location: Estonia
TmEE
Looks like this has fallen into cracks lol (I'm not in actual hurry, I only now remembered to check up on this)
Post 24 Sep 2019, 16:33
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 16850
Location: In your JS exploiting you and your system
revolution
Yeah, I thought some time back that it would be a week till I got back to my dev system. But the 737MAX thing has turned into a really big problem. I should refrain from predicting an end time. As it looks now it might be never. Sigh.

For your suggestion of DV (which I only saw now). You can use a macro to do the CPU specific requirements. It isn't part of the instruction set so I think making special assembler directives isn't the proper place to have it.
Code:
macro DV pointer {
  dw pointer + 1
}    
Post 24 Sep 2019, 23:24
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murder



Joined: 03 Nov 2011
Posts: 8
murder
Is it planned to add support for the ELF64? It`s need for Android programming.
Post 02 Nov 2019, 16:14
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 16850
Location: In your JS exploiting you and your system
revolution
murder wrote:
Is it planned to add support for the ELF64?
I hope so. I am anxious to get back to my dev system soon.
Post 02 Nov 2019, 16:20
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guignol



Joined: 06 Dec 2008
Posts: 631
guignol
woo-ooh !
Post 02 Nov 2019, 19:33
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guignol



Joined: 06 Dec 2008
Posts: 631
guignol
You know, I think Boeing should release all of its software opensource
Post 02 Nov 2019, 20:52
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ProMiNick



Joined: 24 Mar 2012
Posts: 374
Location: Russian Federation, Sochi
ProMiNick
revolution, if thou going back to dev system please cut off optimization mov ->unpaired movw (unpaired with movt) - reason relocations respect only movw movt pair.
Post 02 Nov 2019, 23:19
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 16850
Location: In your JS exploiting you and your system
revolution
ProMiNick wrote:
revolution, if thou going back to dev system please cut off optimization mov ->unpaired movw (unpaired with movt) - reason relocations respect only movw movt pair.
Currently fasmarm doesn't generate relocations. If it did then it would still be up to the programmer to create the movw/movt pair manually. A single mov doesn't generate any relocation, so changing it to movw shouldn't have any affect to relocations. Unless I misunderstand what you are suggesting?
Post 03 Nov 2019, 03:28
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