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> Main > APX instructions in FASM 1 and/or 2? |
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sylware 12 Sep 2026, 11:48
Does this first APX include the upgrade to 32 registers?
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ground 23 Sep 2026, 09:15
Yes, there are no multiple versions of APX. So, the 32 registers are available in the first release. The normal 1-byte prefix for 64-bit assembly code will get a 2-byte prefix for APX. That will increase the code size, however, the new 3 operand instructions will compact the code.
For instance when you have a value in RCX and you want to bitshift right 4 times the value and put it in R18, you can do in APX: SHR R18, RCX, 4 It will not touch the RCX register. Intel has a simulator for APX. Are there any initiatives to motivate big G. Thomasz to think about APX? |
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sylware 23 Sep 2026, 11:09
APX is basically RISC-V/ARM for x86_64.
Funny. Maybe we'll get a RISC-V decoder front-end for AMD and INTEL µarchitectures (probably server/mobile at first) Yep, maybe the time fasm pre-processor/CALM languages will get a RISC-V port is getting closer? |
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