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> Main > Interesting notes from Matt Godbolt |
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Mаt Quasar 05 Dec 2025, 09:19
Matt Godbolt wrote: Unlike other partial register writes, when writing to an e register like eax, the architecture zeros the top 32 bits for free. So xor eax, eax sets all 64 bits to zero. How so? He says nobody uses "xor rax,rax", just "xor eax,eax" is enough even for 64-bit. https://xania.org/AoCO2025 (Advent of Compiler Optimisations 2025) Quote: This December will be the Advent of Compiler Optimisations: I’ll release one blog post and video each day, each detailing a fun and interesting C or C++ optimisation that your compiler can do. I’ll go into the details of when it applies, how to interpret the assembly, and perhaps as importantly, when it doesn’t apply. |
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05 Dec 2025, 09:19 |
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Tomasz Grysztar 05 Dec 2025, 09:46
Mаt Quasar wrote:
In short: Tomasz Grysztar wrote: ...any instruction that targets the 32-bit register, clears the upper 32 bits of the 64-bit register that contains it. This is a general rule, even the "xchg eax,eax" will clear the upper 32 bits of RAX register. I also recall that I needed to ask someone with early access to actual AMD64 hardware to test some instruction encodings that I had doubts about when reading the initial versions of the manual. Among them was the test of NOP in long mode, because previously NOP was just understood to be the same as "xchg eax,eax", but in the long mode such XCHG instruction is no longer a no-operation, as it clears the high bits of RAX! |
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05 Dec 2025, 09:46 |
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Mаt Quasar 05 Dec 2025, 09:55
Thanks @Tomasz! I am late comer! So this is no mystery. It is silly I use mov rax, SYSCALL_NO in my hexdump for Linux x64.
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05 Dec 2025, 09:55 |
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Mаt Quasar 05 Dec 2025, 10:14
Tomasz Grysztar wrote: (and years later I also wrote about it in my article for Paged Out! #1). Noted with thanks. PDF extracted for anyone's convenience.
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05 Dec 2025, 10:14 |
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