NOP under use64

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LocoDelAssembly
Your code has a bug

Joined: 06 May 2005
Posts: 4624
Location: Argentina

LocoDelAssembly 18 Dec 2006, 14:05

Quote:

NOP No Operation
Does nothing. This one-byte instruction increments the rIP to point to next instruction
in the instruction stream, but does not affect the machine state in any other way.
The NOP instruction is an alias for XCHG rAX,rAX.
Related Instructions
None
rFLAGS Affected
None
Exceptions
None
NOP

So, why fasm encodes "XCHG rAX,rAX" as 48 90? Note that under use32 a "XCHG eAX,eAX" is just 90 and "XCHG AX,AX" under use16 is 90 too.

18 Dec 2006, 14:05

Tomasz Grysztar

Joined: 16 Jun 2003
Posts: 8351
Location: Kraków, Poland

Tomasz Grysztar 18 Dec 2006, 14:20

This is from AMD manuals - by rAX they don't mean there the RAX register, but the register of selected size, for example in description of DIV instruction they use names rDX and rAX that mean any of the DX:AX, EDX:EAX, RDX:RAX pairs (which one, depends on the mode and prefix).
In 64-bit mode 32-bit is the default, thus NOP is an alias for XCHG EAX,EAX, but... not really! That's because 90h does really nothing, while the real XCHG EAX,EAX does clear upper bits of RAX - that's why XCHG EAX,EAX is encoded in a different way, too.

Last edited by Tomasz Grysztar on 18 Dec 2006, 14:23; edited 1 time in total

18 Dec 2006, 14:20

MazeGen

Joined: 06 Oct 2003
Posts: 977
Location: Czechoslovakia

MazeGen 18 Dec 2006, 14:22

Oh, Tomasz, you are beaten to dead in this section! Wink

First, 0x90 would be XCHG EAX, EAX in 64-bit mode so it would clear upper 32 bits.
Second, NOP is not an alias for XCHG rAX, rAX. NOP is independent from rAX register, at least in 64-bit mode. It is mentioned somewhere in the optimization manual.

So I think FASM behaves correctly in this case.

EDIT: heh, we have posted at the same time Smile

18 Dec 2006, 14:22

Tomasz Grysztar

Joined: 16 Jun 2003
Posts: 8351
Location: Kraków, Poland

Tomasz Grysztar 18 Dec 2006, 14:25

Yes, I already added the thing about XCHG EAX,EAX above, here's the quote from description of XCHG instruction in AMD manual:

Quote:

The x86 architecture commonly uses the XCHG EAX, EAX instruction (opcode 90h) as
a one-byte NOP. In 64-bit mode, the processor treats opcode 90h as a true NOP only if
it would exchange rAX with itself. Without this special handling, the instruction
would zero-extend the upper 32 bits of RAX, and thus it would not be a true nooperation.
Opcode 90h can still be used to exchange rAX and r8 if the appropriate
REX prefix is used.

And thus in use64 mode fasm encodes XCHG EAX,EAX as 87-C0, and XCHG EAX,R8D as 41-90.

PS. MazeGen: we did talk about this in Kraków, didn't we? Wink

18 Dec 2006, 14:25

MazeGen

Joined: 06 Oct 2003
Posts: 977
Location: Czechoslovakia

MazeGen 18 Dec 2006, 14:31

Quote:

In 64-bit mode, the processor treats opcode 90h as a true NOP only if
it would exchange rAX with itself.

Shouldn't it be the following? It applies only to XCHG EAX,EAX.

Quote:

In 64-bit mode, the processor treats opcode 90h as a true NOP only if
it would exchange EAX with itself.

18 Dec 2006, 14:31

Tomasz Grysztar

Joined: 16 Jun 2003
Posts: 8351
Location: Kraków, Poland

Tomasz Grysztar 18 Dec 2006, 14:47

I understand it as they mean here that 66-90 and 48-90 also behave like a true NOP.

18 Dec 2006, 14:47

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