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flat assembler > Main > New instructions

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Bargest



Joined: 09 Feb 2012
Posts: 64
Location: Russia
New instructions
Here (or here) I found "AMD64 Architecture Programmer's Manual Volume 3: General Purpose and System Instructions"
There are several instructions, that are not supported by FASM. For example: BLCMSK, BLCI, BLCIC, BLCFILL, BLSMSK, BLSFILL...
I hope one day they will be included in FASM.Smile[/url]

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Post 14 Mar 2012, 13:08
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Tomasz Grysztar
Assembly Artist


Joined: 16 Jun 2003
Posts: 5459
Location: Kraków, Poland
I consider it to be a "XOP2" extension, so I will implement it alongside the AVX2 instructions. So you should expect it in fasm 1.70.
Post 14 Mar 2012, 13:21
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rugxulo



Joined: 09 Aug 2005
Posts: 1953
Location: Usono (aka, USA)
Do any cpus have such instructions yet? Pardon my hubris, but it seems a bit silly to support instructions for a computer that hasn't even been manufactured, much less sold. Remember how everyone jumped on AMD's SSE5, and then it was dropped/changed incompatibly? Even AVX (shipped 2011) seems ultra new since almost nobody has it yet. Ah well, guess you can't keep bloat^H^H^H^H^H progress down. Smile
Post 14 Mar 2012, 18:36
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Tomasz Grysztar
Assembly Artist


Joined: 16 Jun 2003
Posts: 5459
Location: Kraków, Poland
Rest assured that I do not hurry needlessly.

As for that SSE5 story, I may even say "Yeah, I saw that coming." Wink
Post 14 Mar 2012, 18:49
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peter



Joined: 09 May 2006
Posts: 63
Rugxulo, there is an emulator that allows you to try AVX2 instructions without having a processor supporting them. YASM already generates the new instructions; it would nice if FASM supported them, too.
Post 16 Mar 2012, 05:46
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smiddy



Joined: 31 Oct 2004
Posts: 471
peter have you used this emulator? A quick glance it looks like a code inspector more than say a virtual machine. Is that correct?
Post 16 Mar 2012, 11:03
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Alphonso



Joined: 16 Jan 2007
Posts: 294
An emulator and code inspector (see were the action is).

Should really do a bit more with detection but anyway, run on C2D cpu 32-bit OS.

Edit: and check syntax. My bad, thanks Tomasz.


Description:
Filesize: 21.07 KB
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lzcnt1.png




Last edited by Alphonso on 16 Mar 2012, 14:52; edited 1 time in total
Post 16 Mar 2012, 14:05
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Tomasz Grysztar
Assembly Artist


Joined: 16 Jun 2003
Posts: 5459
Location: Kraków, Poland
"db 0f4h,0fh,0bdh,0d0h" is "lzcnt edx,eax", not "lzcnt eax,edx". Try how fasm assembles it.
Post 16 Mar 2012, 14:22
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 12125
Location: Another plane of existence
My CPU supports lzcnt natively. No need for sde. Perhaps a better test would be with a BLC* instruction.
Post 16 Mar 2012, 15:14
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Tomasz Grysztar
Assembly Artist


Joined: 16 Jun 2003
Posts: 5459
Location: Kraków, Poland
Well, LZCNT was part of SSE4a, so AMD processors have it since long. But now Intel decided to adopt it.
Post 16 Mar 2012, 15:17
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Alphonso



Joined: 16 Jan 2007
Posts: 294
Sigh, how about BZHI then. Sad


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bzhi.png


Post 16 Mar 2012, 16:04
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