Here (or here) I found "AMD64 Architecture Programmer's Manual Volume 3: General Purpose and System Instructions"
There are several instructions, that are not supported by FASM. For example: BLCMSK, BLCI, BLCIC, BLCFILL, BLSMSK, BLSFILL...
I hope one day they will be included in FASM.[/url]

I consider it to be a "XOP2" extension, so I will implement it alongside the AVX2 instructions. So you should expect it in fasm 1.70.

Do any cpus have such instructions yet? Pardon my hubris, but it seems a bit silly to support instructions for a computer that hasn't even been manufactured, much less sold. Remember how everyone jumped on AMD's SSE5, and then it was dropped/changed incompatibly? Even AVX (shipped 2011) seems ultra new since almost nobody has it yet. Ah well, guess you can't keep bloat^H^H^H^H^H progress down.

Rest assured that I do not hurry needlessly.

As for that SSE5 story, I may even say "Yeah, I saw that coming."

Rugxulo, there is an emulator that allows you to try AVX2 instructions without having a processor supporting them. YASM already generates the new instructions; it would nice if FASM supported them, too.

peter have you used this emulator? A quick glance it looks like a code inspector more than say a virtual machine. Is that correct?

An emulator and code inspector (see were the action is).

Should really do a bit more with detection but anyway, run on C2D cpu 32-bit OS.

Edit: and check syntax. My bad, thanks Tomasz.

"db 0f4h,0fh,0bdh,0d0h" is "lzcnt edx,eax", not "lzcnt eax,edx". Try how fasm assembles it.

My CPU supports lzcnt natively. No need for sde. Perhaps a better test would be with a BLC* instruction.

Well, LZCNT was part of SSE4a, so AMD processors have it since long. But now Intel decided to adopt it.

Sigh, how about BZHI then.