Intel released SSE4 documentation

Seems like a lot of fun to add the DREX support into fasm

SSE5 introduces the DREX prefix byte which is similar to the REX prefix byte that AMD introduced with AMD64. Note that none of the SSE's including SSE4 introduce any prefix bytes.

SSE5 also adds genuine 3-way insructions with two sources and an independent destination. None of the SSE's including SSE4 have 3-way instructions.

SSE5 has conditional moves. Again, no conditional moves in SSE including SSE4.

SSE5 is a true ISA extension that matches a lot of the power of advanced instruction sequences like what is available on Itanium or what was available with Altivec on the G5 Macs.

SDK for 45nm Next Generation Intel® Core™2 Processor Family and Intel® SSE4 (Penryn SDK): A collection of documentation and tools for developing software for Penryn and Intel SSE4. The Penryn SDK includes presentations and whitepapers on Penryn and Intel SSE4, and an Intel SSE4 emulator that allows you to start developing applications with Intel SSE4 today!

Imagine CRC32 calculation or strlen in hardware .

CRC32 instruction for 64-bit source operand and 64-bit destination operand:
TEMP1[63-0] = BIT_REFLECT64 (SRC[63-0])
TEMP2[31-0] = BIT_REFLECT32 (DEST[31-0])
TEMP3[95-0] = TEMP1[63-0] << 32
TEMP4[95-0] = TEMP2[31-0] << 64
TEMP5[95-0] = TEMP3[95-0] XOR TEMP4[95-0]
TEMP6[31-0] = TEMP5[95-0] MOD2 11EDC6F41H
DEST[31-0] = BIT_REFLECT (TEMP6[31-0])
DEST[63-32] = 00000000H

CRC32 instruction for 32-bit source operand and 32-bit destination operand:
TEMP1[31-0] = BIT_REFLECT32 (SRC[31-0])
TEMP2[31-0] = BIT_REFLECT32 (DEST[31-0])
TEMP3[63-0] = TEMP1[31-0] << 32
TEMP4[63-0] = TEMP2[31-0] << 32
TEMP5[63-0] = TEMP3[63-0] XOR TEMP4[63-0]
TEMP6[31-0] = TEMP5[63-0] MOD2 11EDC6F41H
DEST[31-0] = BIT_REFLECT (TEMP6[31-0])

CRC32 instruction for 16-bit source operand and 32-bit destination operand:
TEMP1[15-0] = BIT_REFLECT16 (SRC[15-0])
TEMP2[31-0] = BIT_REFLECT32 (DEST[31-0])
TEMP3[47-0] = TEMP1[15-0] << 32
TEMP4[47-0] = TEMP2[31-0] << 16
TEMP5[47-0] = TEMP3[47-0] XOR TEMP4[47-0]
TEMP6[31-0] = TEMP5[47-0] MOD2 11EDC6F41H
DEST[31-0] = BIT_REFLECT (TEMP6[31-0])

CRC32 instruction for 8-bit source operand and 64-bit destination operand:
TEMP1[7-0] = BIT_REFLECT8(SRC[7-0])
TEMP2[31-0] = BIT_REFLECT32 (DEST[31-0])
TEMP3[39-0] = TEMP1[7-0] << 32
TEMP4[39-0] = TEMP2[31-0] << 8
TEMP5[39-0] = TEMP3[39-0] XOR TEMP4[39-0]
TEMP6[31-0] = TEMP5[39-0] MOD2 11EDC6F41H
DEST[31-0] = BIT_REFLECT (TEMP6[31-0])
DEST[63-32] = 00000000H

CRC32 instruction for 8-bit source operand and 32-bit destination operand:
TEMP1[7-0] = BIT_REFLECT8(SRC[7-0])
TEMP2[31-0] = BIT_REFLECT32 (DEST[31-0])
TEMP3[39-0] = TEMP1[7-0] << 32
TEMP4[39-0] = TEMP2[31-0] << 8
TEMP5[39-0] = TEMP3[39-0] XOR TEMP4[39-0]
TEMP6[31-0] = TEMP5[39-0] MOD2 11EDC6F41H
DEST[31-0] = BIT_REFLECT (TEMP6[31-0])

Notes:
BIT_REFLECT64: DST[63-0] = SRC[0-63]
BIT_REFLECT32: DST[31-0] = SRC[0-31]
BIT_REFLECT16: DST[15-0] = SRC[0-15]
BIT_REFLECT8: DST[7-0] = SRC[0-7]
MOD2: Remainder from Polynomial division modulus 2    

Bit reflection is used in all CRC32 algorithms, so it's not unusual.

What's actually bad is that they used polynomial 11EDC6F41 from iSCSI standard. Another polynomial (EDB88320, reflected 04C11DB7) is used in almost all programs (WinZip, WinRar, WinHex, etc).