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flat assembler > Main > Adjusting Initial Thread Stack Address(...?)

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vivik



Joined: 29 Oct 2016
Posts: 174
Adjusting Initial Thread Stack Address(...?)
I found this article by randomly googling "thread stack address".

https://software.intel.com/en-us/articles/adjusting-thread-stack-address-to-improve-performance-on-intel-xeonr-processors

I don't get it. They recommend wasting space on stack for some reason, in multithreaded apps? I haven't heard anything like that before. Is this real?

"Two threads with very similar stack frame images and access patterns to local variables on the stack are very likely to cause alias conflicts resulting in significant performance degradation."
Post 30 Jul 2017, 20:05
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AsmGuru62



Joined: 28 Jan 2004
Posts: 1386
Location: Toronto, Canada
Maybe this one:
https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html
3.6.7 Stack Alignment

At some point it talks about the stalls happening when code mixes store/loads with addresses, which are different by a MULTIPLE of 4Kb. Usually stack frames are different by these values.
Post 30 Jul 2017, 20:29
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 15181
Location: GW170817
Probably their concern is with caching. The number of sets/ways of the cache subsystem can cause aliasing problems (i.e. thrashing) when you have accesses that align in multiples of the cache geometry. Note that the cache thrashing can apply to one or both of 1) the "normal" memory cache, and 2) the TLB cache.
Post 30 Jul 2017, 22:18
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vivik



Joined: 29 Oct 2016
Posts: 174
The first link mentions counting "the number of 64KB alias events". Is it possible to actually receive and count them? How?
Post 31 Jul 2017, 07:05
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