Joined: 24 Aug 2004
Location: Crossing the Cauchy horizon
Probably their concern is with caching. The number of sets/ways of the cache subsystem can cause aliasing problems (i.e. thrashing) when you have accesses that align in multiples of the cache geometry. Note that the cache thrashing can apply to one or both of 1) the "normal" memory cache, and 2) the TLB cache.
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