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Index > Compiler Internals > BLENDVPS/BLENDVPD/PBLENDVB syntax

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MazeGen



Joined: 06 Oct 2003
Posts: 977
Location: Czechoslovakia
MazeGen
fasm requires the source xmm0 implicate register to be declared explicitly for the following instructions:
Code:
blendvps xmm1, xmm2, xmm0
blendvpd xmm1, xmm2, xmm0
pblendvb xmm1, xmm2, xmm0    

I'm not sure if this follows Intel syntax.

Intel manuals don't help here:
Quote:
<XMM0>: indicates implied use of the XMM0 register. ...
Some instructions use the XMM0 register as the third source operand, indicated
by <XMM0>. The use of the third XMM register operand is implicit in the instruction
encoding and does not affect the ModR/M encoding.

These cases are similar to the following instructions I think:
Code:
mul cl ; implicate source AL register
rdmsr ; implicate source ECX register
pcmpestrm xmm1, xmm2, 0 ; implicate source rAX and rDX registers    

It seems to me that anytime the implicated source operand is fixed and the syntax is unambiguous, implicate operand is missing in the syntax.

(SHL AX, CL needes CL to be declared because SHL AX, imm is allowed as well.)

What do you think?


Last edited by MazeGen on 17 Jul 2009, 09:32; edited 1 time in total
Post 16 Jul 2009, 07:25
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Madis731



Joined: 25 Sep 2003
Posts: 2140
Location: Estonia
Madis731
I first thought about it, but then stick to the "FASM convention" Smile
Post 16 Jul 2009, 08:34
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Tomasz Grysztar



Joined: 16 Jun 2003
Posts: 7739
Location: Kraków, Poland
Tomasz Grysztar
The problem is, that Intel manuals have changed over time in this aspect - and there were some inconsistencies that fasm borrowed from there, though they now seem to be corrected. The example is "monitor" and "mwait" instructions, for which fasm still uses the old "monitor eax,ecx,edx" and "mwait eax,ecx" syntax, while current Intel manuals list them as having no explicit operands.

Therefore it would perhaps be nice to clean this up in fasm as well - perhaps just allow syntax without those redundant operands, and keep the old syntax for compatibility?

So, current list of instructions to correct is: blendvps, blendvpd, pblendvb, monitor and mwait. Do you know any more, that I forgot?
Post 28 Jul 2009, 07:12
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MazeGen



Joined: 06 Oct 2003
Posts: 977
Location: Czechoslovakia
MazeGen
Quote:
Therefore it would perhaps be nice to clean this up in fasm aswell - perhaps just allow syntax without those redundant operands, and keep the old syntax for compatibility?


I like this idea.

Quote:
So, current list of instructions to correct is: blendvps, blendvpd, pblendvb, monitor and mwait. Do you know any more, that I forgot?


This list should be complete - the other (older) instructions have clearer syntax.

I'm fighting with Intel manuals as well. It seems to me that Intel's race with AMD and GPUs forced confusion and bugs in the manuals. They should get more time to clean things up.

And we can't check SSE4 instructions agains AMD manuals because AMD doesn't support SSE4, at least for now Sad
Post 28 Jul 2009, 07:29
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Madis731



Joined: 25 Sep 2003
Posts: 2140
Location: Estonia
Madis731
Actually there were cases with FPU instructions st0 or st(0) and implicit or explicit a few years ago.
I don't deal with FPU any more because SSE replaces most of the instructions with better variants.
Post 28 Jul 2009, 10:35
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Tomasz Grysztar



Joined: 16 Jun 2003
Posts: 7739
Location: Kraków, Poland
Tomasz Grysztar
1.69.03 has both the syntaxes allowed.
Post 03 Aug 2009, 09:42
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