mov     ax,7202h
    push    ax
  popf
        pushf        ; Unpredictable effect ???
     pop     bx
  cmp     ax,bx
       je      processor_ok ; >=80386
    

   mov     ax,sp         
   push    sp            ; 86/186 will push sp-2
   pop     cx            ; others will push sp
   cmp     ax,cx
   je      cpu_286    ; if >=80286
    

EFLAGS Pushed on the Stack:
8086 processor—bits 12 through 15 are always set.
Intel 286 processor—bits 12 through 15 are always cleared in real-address mode.
32-bit processors in real-address mode—bit 15 (reserved) is always cleared, and bits 12 through 14 have the last value loaded into them.

Imho, why even bother with 386 detection these days? People that still run hardware that old will very likely know what they're doing.

Is it correct that this code will return junk when running in "V86" ?

YES. They are very clear. Works only in real mode as said

In short, call int 2Fh,1687h

=======================
proper 8086 detection
=======================


SHR with values does indeed work on 80186 so you need to test for earlier CPUs first.

All later CPUs mask the CL register with 0Fh, when shifting a byte by cl bits. This test loads CL with a large value (20h) and shifts the AX register right. With the 8088, any bits in AX are shifted out, and becomes 0. On all higher level processors, the CL value of 20h is anded with 0Fh, before the shift. This means the effective number of shifts is 0, so AX is unaffected.

Code:

        mov     cl, 20h            ; load high CL value
        mov     ax, 1              ; load a non-zero value in AX
        shr     ax, cl             ; do the shift 
        cmp     ax, 0              ; if zero, then 8088/86
    

It is now either a V20/V30 or a 8088. But which one? Here's an undocumented trick: On the 8088, 0Fh performs a POP CS. On the V20/V30, it is the start of a number of multi-byte instructions. With the byte string 0Fh, 14h, C3h the CPU will perform the following:

Code:

;       8088/8086               V20/V30
        pop     cs              set1   bl, cl  
        adc     al, 0C3h 
    

So we can exploit that:

Code:

        xor     al, al             ; clear al and carry flag 
        push    cs
        db      0Fh, 14h, 0C3h     ; instructions (see above explanation)
        cmp     al, 0C3h           ; if al is C3h then 8088/8086 
        jne     upV20
        mov     ax, 0              ; set 8088/8086 flag
        jmp     Exit

upV20:
        pop     ax                 ; correct for lack of pop cs 
        mov     ax, 200h           ; set V20/V30 flag
        jmp     Exit
    

Past that, you can continue to test for the 80186: Check what is pushed onto the stack with a PUSH SP instruction. The 80186 updates the stack pointer before the value of SP is pushed onto the stack. With all higher level processors, the current value of SP is pushed onto the stack, and then the stack pointer is updated.

Code:

up186:  
        mov     bx, sp             ; save the current stack ptr 
        push    sp                 ; do test
        pop     ax                 ; get the pushed value
        cmp     ax, bx             ; did SP change ? 
        je      up286              ; if not, it's a 286+, so start
                                   ;    testing for that
        mov     ax, 1              ; set 80186 flag
        jmp     Exit 
    

Hope that helps!

Trixter
mobygamer()gmail.com

CPU/FPU Feature Detection Library
Recognizes 20+ CPUs and about 15 FPUs, checks for V86,
determines CPU clock speed and determines 386dx chip stepping.
ASM/PAS/C[++] sources included! Windows, OS/2 & DESQview-aware:
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and DESQview! DPMI-compatible. Make batches provided.
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FASM 1.0 used to test the correct way (but failed to jump then ???)

maybe I have correct code now ... but still no 16-bit CPU to test