Hi vid,
yep, basically it's true, the cpu's vary a lot in all these devices (PDA, phone, etc.), but they are all based on the same architecture. Normally all these companies license the architecture/design from ARM (www.arm.com) and then build the cpu's as ARM themselves doesn't produce any hardware themselves.
These architectures have a great variety and are enhanced all the time, but normally within some limits the compatibility is there. Before long time (ARM600) for example there was a 26bit-mode, nowdays the XScale only supported 32bit-mode, so when you go to far back in ARM-history there are some differences. ARM themselves number the architecture, so the XScale is based on ARMv5TE-architecture, where 5 means the evolution number and T is for an added 'Thumb'-instruction core (16 bit sized instruction to save memory) and E for a kind of DSP-like MMX extention.
Recently there are more things added to the core, like SIMD instructions, or a JAZCELL, supporting JAVA byte code...
http://www.arm.com/products/CPUs/architecture.html
...but of course you always have to look, what the cpu-producing company (Intel, Samsung,...) is actually using of these offers from ARM...
I mainly coded on my Risc PC, using the core 26/32 bit cpu, that code is I think valid for all the later CPU's, except the 26-bit thing...the first thing to know that all instructions have a length of 32-bit (in ARM coding 32-bit was always related to 1 word, not like DWORD in x86 coding, as ARM was always 32-bit RISC).
What I like most is the following stuff of it:
- 16 registers (0 to 12 general purpose, R13 stackpointer, R14 Linkregister, R15 program counter)
- extensive use of conditioned execution on all commands (not only mov) ike:
Code: |
cmp r0, #10
movgt r0, #0
movle r0, #1
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- doing multiple stuff with one instruction like:
Code: |
add r0, r0, [r1, LSL #5]
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...what means r0=r0 + (r1<<5).
and storing/loading multiple words:
...this one stores r1 to r8 (8*32 bit data) at r0 and after storing (IA) increments the address (r0), so that you can easily do a memory copy loop without the need of an add r0,r0,#256.
The instruction set is really RISC-like limited, but actually I never felt limited, except of the missing FPU, even the missing DIV can be worked around normally with MUL by 1/x. The XScale/StrongARM has also the extension of a 64bit-MUL.
Downside of the CPU's:
- No FPU (except the new multimedia extensions)
- No DIV instruction
- Memory/Video Memory access slow compared to general desktop x86 architecture
- No second level cache
All this is only as far as I know...the ARM world is big

...it's the most sold 32bit-CPU on the world (think of all the Advance/DS Nintendo Gamboys). Sometimes I've seen demo-coding for the gameboy, but I don't know about their developement tools, fur sure ARM company itself has lots of may be commercial tools.
When it comes to OS-coding may be it get's difficult to get hand on a decent tool or information for all the mobile phones...don't got any experience with other OS than the Risc OS 4.