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> Compiler Internals > [fasm2] Add instructions, tests and fixes to iset: |
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bitRAKE 02 Nov 2026, 22:00
New instructions:
AMD: SVM, SEV-SNP, MONITORX/CLZERO/INVLPGB/RDPRU/MCOMMIT, SSE4a, 3DNow! extensions, XOP/FMA4/TBM/LWP (the encoder now emits the 8Fh lead byte). Intel vector: VNNI/IFMA (VEX and EVEX), VNNI-INT8/16, BF16/AVX-NE-CONVERT, SHA512, SM3/SM4, VP2INTERSECT, AMX-FP16/COMPLEX, 4FMAPS, and all 106 AVX512-FP16 instructions. Intel scalar/system: CLWB/PREFETCHWT1/PREFETCHI/WBNOINVD, PTWRITE/PCONFIG/ENCLV/VMFUNC, RAO-INT, FRED/LKGS, TDX, MSRLIST/WRMSRNS/USER_MSR, CMPccXADD. Vendor: PadLock. Notes: All extension instructions are assembly-time gated by USE and line modifier {EXT} forms - see testing for examples. Runtime CPUID gating is documented at the top of all extension files, example: Code: ; CPUID requirements ("use <setting>" to enable, or "use everything"): ; ; setting CPUID bit instructions ; SEV_SNP 8000_001Fh:EAX[4] pvalidate rmpadjust rmpupdate psmash ; RMPQUERY 8000_001Fh:EAX[6] rmpquery Fixed Instructions. [edit] APX integration is done, but I need to cross verify tools reporting different things. I went with simple mnemonics with pre-/post- mnemonic modifier semantics that seemed logical. Code: {rex2} popcnt eax, ecx {evex} andn eax, ebx, ecx bextr {nf} eax, ebx, ecx ccmpg {dfv=cf,of} [rax], bl imul {zu} ax, bx, 10 The layered strategy being used added ~10% to assemble-time; but it can be flattened. I'm aiming for correctness first. _________________ ¯\(°_o)/¯ AI understands the way 2+2 understands 4. |
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02 Nov 2026, 22:00 |
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Tomasz Grysztar 03 Nov 2026, 11:41
For opcode testing I normally use my IEV framework. Every time I implemented a new instruction set, I've been left with many test references, unfortunately I've lost most of them from the earlier staged of fasm development, it was only relatively recently that I started to handle them with more care.
The test I use are not only for correctness, but also for fasm's optimizations. I have tests for specific boundary conditions, like: Code: use32 inc dword [ds:ebp+ebp+7Fh] ; 3E FF 44 2D 7F inc dword [ds:ebp+ebp+80h] ; FF 04 6D 80 00 00 00 use64 mov eax,[gs:30h] ; 65 67 A1 30 00 00 00 mov eax,[gs:000000000FFFFFFFFh] ; 65 67 A1 FF FF FF FF mov eax,[gs:0FFFFFFFFFFFFFFFFh] ; 65 8B 04 25 FF FF FF FF mov eax,[gs:0CCCCCCCCCCCCCCCCh] ; 65 A1 CC CC CC CC CC CC CC CC |
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03 Nov 2026, 11:41 |
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bitRAKE 03 Nov 2026, 21:55
This latest update has full corpus based on IEV - both pass and fail cases - including implementation and absent instructions/forms. The tooling xref is quite extensive: spec, XED, gcc, clang, ... Yet, nothing has been run on real hardware or an emulator (they tend to increase the error surface rather than proof anything).
APX is in a somewhat complete state. Next on the roadmap is AVX10.2. _________________ ¯\(°_o)/¯ AI understands the way 2+2 understands 4. |
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03 Nov 2026, 21:55 |
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bitRAKE 09 Nov 2026, 00:28
I told the AI to created an optimized projection of XED x86 information that aligns with fasmg's x86-2.inc -- here is the drop-in replacement. It used a SAT solver to produced optimized tables for the instructions, and probing against fasmg to engineer the syntax for optimal performance.
It's 41227 lines of slop that is quite performant. Quote: The include costs about 0.017 s more than x86-2.inc on every pass. Lines save about 2 µs each, so a program of about 8,000 lines breaks even. |
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09 Nov 2026, 00:28 |
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