Usually is it better to have a loop in less than a cache line working on a one byte load or a much bigger loop probably on 2 cache lines working on a full register load but with a bit of branchless convolution in order to keep only one conditional branch (sorta loop unrolling over the bytes of one register)?

No way to know without testing. Each CPU/system/OS is different in how it performs, and each code/data combo performs differently depending upon many variables.

It depends; if you are using string operations (e.g, movs, stos), assuming "whatever" is somewhat okay because those operations are optimized internally in many modern chips.

Regarding the latter it depends, the branch cost is also a thing you must account, and reducing stuff to a single branch usually is the optimal (depends on your case, you must account yourself). Regarding two memory loads, it depends, cache-misses aren't all equally bad. If you miss data in L1 but it is in L2, or miss in L2 and it is in L3, all have manageable costs; they being usually small enough to tolerate or you being able of amortizing them somehow.

Which is better will always depend on the case, as previously mentioned, the cost depends on the cache position. Therefore, I think that the best might be to keep it tight in a single line: less risk. And when I say "less risk" it is because the layer of the line is always uncertain, at most it is likely.

Yet it all depends on your case. Also, branch costs are decreasing the more they are hit on CPUs with branch prediction; so it may not be as problematic as the memory thing.

Either way, there is a chance that the difference between the two things you mentioned end up with equal or very similar costs, depends on what you're doing and how either way.

You must also be aware that larger word instructions add less load onto the pipeline, so it can be easier for the chip to run.

Those "string"/"memory manipulation" loops are really ubiquitous, and it seems there is no µarchitecture common sweet spot way to implement them.

Well, I guess I'll go for loop machine instructions fitting in 1 cache line with the maximum "load" (2/4/8 bytes) I can have with branchless logic in order to keep only one conditional branch fit for the classic prediction rule (misprediction penalty at loop exit only).

But with 2 cache lines of machine instructions I should be able to fit branchless logic for a 8bytes load for many of such loops.

meh.