register renaming cost

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sylware

Joined: 23 Oct 2020
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Location: Marseille/France

sylware 24 Sep 2026, 13:21

On modern micro-architectures, is there a significant "cost" for register renaming?

Because with APX, machine instructions with a destination register different than the source registers should invade the x86_64 space (and we may get 32 registers).

24 Sep 2026, 13:21

revolution
When all else fails, read the source

Joined: 24 Aug 2004
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Location: In your JS exploiting you and your system

revolution 24 Sep 2026, 13:44

What cost is being measured? Compared to what? Because renaming can't be turned off to measure any difference between off or on.

With regard to "32" registers, that hasn't been valid for a long time. There are more than 200 registers in many CPU cores produced today. Renaming just picks a few out of the pool for each instruction.

24 Sep 2026, 13:44

sylware

Joined: 23 Oct 2020
Posts: 679
Location: Marseille/France

sylware 24 Sep 2026, 14:02

Is this picking has a cost, namely will it cost extra cycles?

24 Sep 2026, 14:02

revolution
When all else fails, read the source

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revolution 24 Sep 2026, 14:28

There are no extra cycles for register allocation, because there is no way to turn it off to compare.

If it takes 100 cycle to allocate a register then that is just how the CPU works. There isn't an alternative path that doesn't do register renaming.

Overall, register renaming is a win (it has many advantages), or otherwise the makers would kill it and boast everywhere how they made the CPU "faster".

24 Sep 2026, 14:28

sylware

Joined: 23 Oct 2020
Posts: 679
Location: Marseille/France

sylware 24 Sep 2026, 15:10

I could code in a way to reduce register renaming pressure. That's why I did ask if there is a cost as extra cycles.

So you say there is none of those extra cycles on modern micro-architectures.

Good!

24 Sep 2026, 15:10

revolution
When all else fails, read the source

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Location: In your JS exploiting you and your system

revolution 24 Sep 2026, 15:21

There aren't any "extra" cycles.

Any cycles taken to pick a register are just how it works. The pipeline might have zero, one, two or a million cycles for the renaming stage. But those aren't "extra" cycles, they are normal cycles. There isn't a way to avoid it. All code is stuck with it. There isn't a way to "code in a way to reduce register renaming pressure" because all code passes through the renaming stage(s).*

* Maybe "nop" is special and can bypass some stages or something, IDK, but nop doesn't do anything that can affect the state of the register set.

24 Sep 2026, 15:21

sylware

Joined: 23 Oct 2020
Posts: 679
Location: Marseille/France

sylware 26 Sep 2026, 10:14

Ok. So register renaming is "always" (i.e. with enough testing) there and has a static cost.

26 Sep 2026, 10:14

revolution
When all else fails, read the source

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revolution 26 Sep 2026, 11:29

sylware wrote:

Ok. So register renaming is "always" (i.e. with enough testing) there and has a static cost.

Have a look at the pipeline diagrams of the CPU. There is a fixed number of stages for renaming. No bypass is available to skip a stage. If such a bypass did exist for a subset of instructions then those instructions jumping ahead would collide with others already ahead of them.

So far, as of today, there is no variable number of cycles where some instructions use X cycles, and others use Y. Perhaps tomorrow a new architecture comes out that changes that?

26 Sep 2026, 11:29

Furs

Joined: 04 Mar 2016
Posts: 2767

Furs 26 Sep 2026, 22:28

revolution wrote:

So far, as of today, there is no variable number of cycles where some instructions use X cycles, and others use Y. Perhaps tomorrow a new architecture comes out that changes that?

Just to be clear he's talking about the same "type" of instruction but different place/execution (e.g. both adds or both subs etc). Cause obviously a div is slower.

26 Sep 2026, 22:28

revolution
When all else fails, read the source

Joined: 24 Aug 2004
Posts: 21154
Location: In your JS exploiting you and your system

revolution 27 Sep 2026, 03:21

Furs wrote:

revolution wrote:
So far, as of today, there is no variable number of cycles where some instructions use X cycles, and others use Y. Perhaps tomorrow a new architecture comes out that changes that?
Just to be clear he's talking about the same "type" of instruction but different place/execution (e.g. both adds or both subs etc). Cause obviously a div is slower.

I was talking about the renaming part of the pipeline. It applies to all instructions, regardless of type.

27 Sep 2026, 03:21

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