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> Main > use32 directive not will add prefix 0x66? |
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Core i7 27 Mar 2026, 15:31
Apparently your disassembler is in 16-bit mode, because this design works correctly.
Code: format binary inc_addr equ 1000h use32 org 0A000h start: mov eax,10h mov ebx,inc_addr mov [ebx],eax ret
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Byte 27 Mar 2026, 18:07
Thanks for the reply.
Core i7 wrote: Apparently your disassembler is in 16-bit mode... Maybe. But isn't the 0x66 prefix in the binary code a sign of using a 32-bit register? Shouldn't the compiler add this prefix to define a 32-bit instruction? |
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Core i7 27 Mar 2026, 18:21
it turns out the other way around - the prefix 0x66 is used if you use 16-bit registers in x32 mode.
Code: format binary use32 start: mov eax,100h mov bx,66h mov word[eax],bx ret ;------------------------ 00000000: B800010000 mov eax, 00000100 00000005: 66BB6600 mov bx, 0066 ;'f' 00000009: 668918 mov [eax], bx 0000000C: C3 ret |
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Core i7 27 Mar 2026, 18:32
By the way, the prefix also works in the opposite direction - if you use 32-bit registers in x16 mode
Code: format binary use16 start: mov eax,100h mov bx,66h mov word[eax],bx ret ;----------------------- 00000000: 66B800010000 mov eax, 00000100 00000006: BB6600 mov bx, 0066 ;'f' 00000009: 678918 mov [eax], bx 0000000C: C3 ret |
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revolution 27 Mar 2026, 20:31
The CPU has modes.
In 32-bit mode all registers are 32-bit without 0x66, and 16-bit with 0x66. In 16-bit mode all registers are 16-bit without 0x66, and 32-bit with 0x66. The disassembler has to be told which mode the CPU is in to correctly disassemble the bytes. CPU modes are changed by writing to CR0 with MOV or SMSW. There is also 64-bit mode (long mode) where the 0x66 prefix can make registers either 32-bit or 16-bit, or do nothing, depending on the instruction. This is not confusing in any way. |
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Byte 27 Mar 2026, 20:38
revolution wrote:
Thank you, now I understand. |
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