Intel AMX extension

Tomasz - great job !!!!!

I have Xeon 6300 series CPUs (entry level server) 6315P, 6369P and they both lack AMX. You need datacenter or AI level Xeon 6 family to run AMX (that is 6700 or 6500 family)
this is the detection code:

Code:

        mov     eax,1
        cpuid
        bt      ecx,26  ; bit 26 XSAVE: XSAVE (and related) instructions are supported by hardware
        jnc     exit

; Software can use CPUID leaf function 0DH to enumerate the bits in XCR0 that the processor supports
        xor     eax,eax
        cpuid
        cmp     eax,0Dh
        jc      exit            ; CPUID with eax=0Dh not available

        xor     ecx,ecx
        lea     eax,[rcx+0Dh]
        cpuid

        mov     ecx,(1 shl 18) or (1 shl 17)    ; Bit 17: TILECFG state.
                                                ; Bit 18: TILEDATA state.
        and     eax,ecx
        cmp     eax,ecx
        jnz     exit
; highest present bit at Xeon 6300 series is bit 9. PKRU state
; bits 17, 18 are zeros
; if your CPU has these bits present, you can enable the AMX in the XCR0

        mov     rax,cr4
        bts     rax,18
; XSAVE and Extended States (OSXSAVE) Bit. Bit 18. If this bit is set to 1 then the operating system
; supports the XGETBV, XSETBV, XSAVE and XRSTOR instructions. The processor will also be able
; to execute XGETBV and XSETBV instructions in order to read and write XCR0. Also, if set, the
; XSAVE and XRSTOR instructions can save and restore the x87 FPU state (including MMX registers),
; the SSE state (YMM/XMM registers and MXCSR), along with other processor extended states
; enabled in XCR0.
        mov     cr4,rax

; CPUID.01H:ECX.OSXSAVE[bit 27]) now should be 1
        mov     eax,1
        cpuid
        bt      ecx,27
        jnc     exit

        xor     ecx,ecx
        xgetbv                          ; get XCR0

        or      eax,(1 shl 18) or (1 shl 17)
; XCR0.TILECFG (bit 17.) : If 1, and if XCR0.TILEDATA is also 1, Intel AMX instructions can be executed and the XSAVE feature set can be used to manage TILECFG.
; XCR0.TILEDATA (bit 18.) : If 1, and if XCR0.TILECFG is also 1, Intel AMX instructions can be executed and the XSAVE feature set can be used to manage TILEDATA.
; !!!!! of course you need to enable more bits than only bits 17, 18 - enable also some lower bits like MMX, SSE, AVX, very likely also ZMM_Hi256, Hi16_ZMM - chapter 2.6. in Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3 System Programming Guide

        xsetbv                          ; set XCR0

note the code needs ring0 privilege but the detection (CPUID part) can be executed also from ring3
you can play with it under UEFI shell if you have AMX capable CPU but your OS is not the most recent one (when the OS does not enable AMX even it is present)