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MaoKo



Joined: 07 May 2019
Posts: 91
Location: Paris/French
MaoKo
Hello! In the 2th gen paging (32-bit with PAE), when you modify a PDPTE the modification take only effect when you reload the intel (I don't known for AMD) internal PDPTE register (PDPTE0,...). And a reload is taken from certain operation:
- modification of certain bit in CR0, CR4
- CR3 reload
I wonder if the first option flush the TLB? In the man, there is nothing that say, for example, when you active CR4.SMEP the (I/D)TLB are flushed. If I could reload without this (potential) flush, it would be very interesting.
Post 19 Mar 2021, 23:22
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MaoKo



Joined: 07 May 2019
Posts: 91
Location: Paris/French
MaoKo
Ha ok I just see that https://www.sandpile.org/x86/coherent.htm . sandpile are really useful Wink. But in the intel man a change to CR0.NW and CR0.CD reload the PDPTR. So I'm wonder again if a reload using this approach invalidate the TLB? I know no way to dump the TLB except with the test register but ...
Post 20 Mar 2021, 01:10
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MaoKo



Joined: 07 May 2019
Posts: 91
Location: Paris/French
MaoKo
I finally found a PC in which I can perform some test. In real hardware it's seem to invalidate whenever PDPTR are reloaded but not always on bochs/qemu.
This is a simple test:
Code:
page_table _pdpt, 1H
    PT_pe _pae_directory_identity, _PE_PRESENT
    PT_pe _pae_empty_1, _PE_PRESENT
    PT_pe _pae_empty_2, _PE_PRESENT
    PT_pe _pae_directory_kernel, _PE_PRESENT
    PT_pe _pdpt, (_PTE_PAT or _PE_READ_WRITE or _PE_PRESENT)
end page_table

page_table _pae_empty_1, 1H
    PT_pe _pae_table_identity_2, _PE_READ_WRITE or _PE_PRESENT
end page_table

page_table _pae_empty_2, 1H
end page_table

page_table _pae_directory_identity, 1H
    PT_pe _pae_table_identity_1, _PE_USER or _PE_READ_WRITE or _PE_PRESENT
    PT_pe _pae_table_identity_2, _PE_USER or _PE_READ_WRITE or _PE_PRESENT
    ;PT_pe _pae_table_identity_3, _PE_USER or _PE_READ_WRITE or _PE_PRESENT
    ;PT_pe _pae_table_identity_4, _PE_USER or _PE_READ_WRITE or _PE_PRESENT
end page_table

page_table _pae_table_identity_1, 1H
    repeat _PAE_TABLE_ENTRY_COUNT
        PT_pe ((0H shl _PAE_PAGE_DIRECTORY_SHIFT) + ((% - 1H) shl _PAGE_TABLE_SHIFT)), _PE_USER or _PE_READ_WRITE or _PE_PRESENT
    end repeat
end page_table

page_table _pae_table_identity_2, 1H
    repeat _PAE_TABLE_ENTRY_COUNT
        PT_pe ((1H shl _PAE_PAGE_DIRECTORY_SHIFT) + ((% - 1H) shl _PAGE_TABLE_SHIFT)), _PE_USER or _PE_READ_WRITE or _PE_PRESENT
    end repeat
end page_table

page_table _pae_directory_kernel, 1H
    PT_pe _pae_table_kernel, _PE_READ_WRITE or _PE_PRESENT
    repeat (_FREE_1_INDEX_RECURSIVE - 1H)
        PT_null
    end repeat
    PT_null
    PT_null
    PT_pe _pae_directory_identity, _PE_READ_WRITE or _PE_PRESENT
    PT_pe _pae_empty_1, _PE_READ_WRITE or _PE_PRESENT
    PT_pe _pae_empty_2, _PE_READ_WRITE or _PE_PRESENT
    PT_pe _pae_directory_kernel, _PE_READ_WRITE or _PE_PRESENT
    PT_pe _pdpt, _PE_READ_WRITE or _PE_PRESENT
end page_table

page_table _pae_table_kernel, 1H
    repeat (((_kernel_end - _KERNEL_VIRTUAL) shr _PAGE_TABLE_SHIFT) + 1H)
        PT_pe (_kernel_physical + ((% - 1H) shl _PAGE_TABLE_SHIFT)), _PE_READ_WRITE or _PE_PRESENT
    end repeat
end page_table

_KERNEL_VIRTUAL = 0C0000000H
_PAE_PAGE_DIRECTORY_POINTER_INDEX = (_PAE_TABLE_ENTRY_COUNT - 1H)
_KERNEL_PDPT_INDEX = 3H
_PDPT_INDEX_RECURSIVE = 4H
_FREE_1_INDEX_RECURSIVE = (_PAE_TABLE_ENTRY_COUNT - 7H)
_FREE_2_INDEX_RECURSIVE = (_PAE_TABLE_ENTRY_COUNT - 6H)
_PTE_INDEX_RECURSIVE_1 = (_PAE_TABLE_ENTRY_COUNT - 5H)
_PTE_INDEX_RECURSIVE_2 = (_PAE_TABLE_ENTRY_COUNT - 4H)
_PTE_INDEX_RECURSIVE_3 = (_PAE_TABLE_ENTRY_COUNT - 3H)
_PTE_INDEX_RECURSIVE_KERNEL = (_PAE_TABLE_ENTRY_COUNT - 2H)
_PAE_RECURSIVE_VIRTUAL = ((_KERNEL_PDPT_INDEX shl _PAE_PAGE_DIRECTORY_POINTER_SHIFT) or (_PAE_PAGE_DIRECTORY_POINTER_INDEX shl _PAE_PAGE_DIRECTORY_SHIFT))
_PAE_PDPT_RECURSIVE_VIRTUAL = (_PAE_RECURSIVE_VIRTUAL or (_PDPT_INDEX_RECURSIVE shl _PAGE_TABLE_SHIFT))
_PDPTE_RESERVED_BIT = ((not _PAGE_OFFSET_MASK) or _PE_PCD or _PE_PWT or _PE_PRESENT)

_pdpt_reserved_current:
    mov ebx, _PAE_PDPT_RECURSIVE_VIRTUAL
_pdpt_reserved:
 ; in: ebx - pgpt table pointer
 ; preserves: eax, ebx, ecx, edx, edi, esi, ebp
    and dword [ebx+000H], _PDPTE_RESERVED_BIT
    and dword [ebx+008H], _PDPTE_RESERVED_BIT
    and dword [ebx+010H], _PDPTE_RESERVED_BIT
    and dword [ebx+018H], _PDPTE_RESERVED_BIT
    ret

_pdpt_read_write_current:
    mov ebx, _PAE_PDPT_RECURSIVE_VIRTUAL
_pdpt_read_write:
 ; in: ebx - pdpt table pointer
 ; preserves: eax, ebx, ecx, edx, edi, esi, ebp
 ; note: useful when write protect enable, update only when _PA_PRESENT is active too
 rept 4H i:0H
 {
    test byte [ebx+(i*8H)], _PE_PRESENT
    jz _pdpt_read_write_#i
    or byte [ebx+(i*8H)], _PE_READ_WRITE
_pdpt_read_write_#i:
 }
    ret

_refresh_pae_cr3:
 ; preserves: ecx, edx, edi, esi, ebp
 ; note: reload of PDPTE internal register (PDPTE0, PDPTE1, PDPTE2, PDPTE3)
    call _pdpt_reserved_current
    mov ebx, cr0
    mov eax, ebx
    test eax, _CR0_NW
    jz _refresh_pae_cr3_disable
    xor eax, _CR0_NW
    jmp _refresh_pae_cr3_update
_refresh_pae_cr3_disable:
    xor eax, _CR0_CD
_refresh_pae_cr3_update:
    mov cr0, eax
    mov cr0, ebx
    jmp _pdpt_read_write_current

_kernel_code:
    mov byte [40000000H], 1H
    mov dword [_PAE_PDPT_RECURSIVE_VIRTUAL+8H], 0H
    mov byte [40000000H], 1H
    call _refresh_pae_cr3
    mov byte [40000000H], 1H ; page fault on real hardward but not on bochs/qemu
    jmp $
    

To be able to self modify the pdpt table and not waste 1G virtual address space I use a kind of mutual recursion. I called this the fifth slot technique Wink.
Post 21 Mar 2021, 04:50
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N-LG



Joined: 14 Feb 2019
Posts: 38
Location: france
N-LG
I do not understand everything, even if I am French too, and above all I did not use paging for my OS, but here: https://discord.com/invite/3XjkM6q there is a French-speaking community that knows about paging
Post 22 Mar 2021, 19:08
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