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flat assembler > Non-x86 architectures > how different are non x86 assemblers/cpus?

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Joined: 29 Oct 2016
Posts: 405
I only know x86 and 6502 assembly, I'm curious what other assemblers exist, and what's different about them. Difference down to bytecode level.

If you want a very compressed overview of 6502, each opcode takes exactly one byte (not counting the actual numbers and addresses, they take extra 1 or 2 (for addresses) bytes when present), and only like 70% of that byte combinations are documented. Some of those undocumented combinations actually do something, sometimes even something useful, but this is merely a side effect of how 6502 was done internally. 6502 cannot do multiplication, but you can still do multiplication through a bunch of binary shifts and additions. You cannot move from memory to memory directly, you must load memory to register, and then store register to memory. Carry flag is heavily used for numbers that take more than one byte. Famicon processor is based on 6502, except with extra transistors for video and audio generation, and with decimal numbers support removed (probably for copyright reasons). People reverse engineered those chips, and made emulator in javascript for it. FCEUX contains a debugger, it's a good way to see this processor in action.

I'm curious what's different about arm, and other processors used in different game consoles and older/modern phones. Don't have the time to study each processor individually. Also, I want to buy a hardware that I'll be able to know everything about, down to every transistor, something I can fix cheap enough.
Post 14 May 2018, 09:12
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Joined: 23 Mar 2014
Posts: 63
Traditional ARM and MIPS have 4-byte-long instructions and can be big- or little-endian.
They are load-store CPUs, that is, there are no memory to memory move/add/etc instructions.
They are very regular/orthogonal CPUs, having very few registers or instructions that are hardwired together (like x86 xlat with bx and al, loop with cx, (i)div with ax and dx, etc).
Both have many 32-bit general-purpose registers (16 in ARM, 32 in MIPS).
ARM has flags. MIPS doesn't.
ARM supports branchless conditional execution of instructions. MIPS doesn't.
Originally both required naturally aligned memory operands.
MIPS memory operands are of the form: register+offset. ARM also has reg1+reg2*scale, AFAIR.
ARM has PC-relative addressing. MIPS doesn't.
ARM may have no divider on chip.
MIPS branches have delay slots.
Modern ARM and MIPS processors are more interesting and powerful. There're more compact ISAs (e.g. Thumb, Thumb2, MIPS16e, microMIPS, nanoMIPS). And 64-bit as well.

Buy the i8051 if you wan to know everything down to a single transistor. Reportedly, the smallest implementation has 2700 gates. The i8086 had some 20000+. MIPS32 - 1 to 5 million as far as I can see. Modern stuff is hopelessly large and complex for a single person to understand fully in any reasonable amount of time.
Here's one compiled table: A History of Microprocessor Transistor Count 1971 to 2013.

I could also write a bit about i8051, i8080/Z80, TMS320C54xx. But really, if you get the right doc/datasheet, you can see most of stuff yourself. There's usually enough overview and tables/diagrams to give you an idea of how things are the same as or different from what you already know.
Post 14 May 2018, 10:33
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Joined: 03 Mar 2010
Posts: 258
Location: Belarus
Raymond has a few series on non-x86 architectures.

Alpha AXP:
The Alpha AXP, part 1: Initial plunge
The Alpha AXP, part 2: Integer calculations
The Alpha AXP, part 3: Integer constants
The Alpha AXP, part 4: Bit 15. Ugh. Bit 15.
The Alpha AXP, part 5: Conditional operations and control flow
The Alpha AXP, part 6: Memory access, basics
The Alpha AXP, part 7: Memory access, loading unaligned data
The Alpha AXP, part 8: Memory access, storing bytes and words and unaligned data
The Alpha AXP, part 9: The memory model and atomic memory operations
The Alpha AXP, part 10: Atomic updates to byte and word memory units
The Alpha AXP, part 11: Processor faults
The Alpha AXP: Part 12: How you detect carry on a processor with no carry?
The Alpha AXP, part 13: On treating a 64-bit processor as if it were a 32-bit processor
The Alpha AXP, part 14: On the strange behavior of writes to the zero register
The Alpha AXP, part 15: Variadic functions
The Alpha AXP, part 16: What are the dire consequences of having 32-bit values in non-canonical form?
The Alpha AXP, part 17: Reconstructing a call stack

MIPS R4000:
The MIPS R4000, part 1: Introduction
The MIPS R4000, part 2: 32-bit integer calculations
The MIPS R4000, part 3: Multiplication, division, and the temperamental HI and LO registers
The MIPS R4000, part 4: Constants
The MIPS R4000, part 5: Memory access (aligned)
The MIPS R4000, part 6: Memory access (unaligned)
The MIPS R4000, part 7: Memory access (atomic)
The MIPS R4000, part 8: Control transfer
The MIPS R4000, part 9: Stupid branch delay slot tricks
The MIPS R4000, part 10: Trampolines and stubs
The MIPS R4000, part 11: More on branch delay slots
The MIPS R4000, part 12: Calling convention
The MIPS R4000, part 13: Function prologues and epilogues
The MIPS R4000, part 14: Common patterns
The MIPS R4000, part 15: Code walkthrough
Post 14 May 2018, 10:50
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Joined: 21 Jul 2003
Posts: 2653
Location: dank orb
68000 was the first assembly language I programmed. Many similarities between x86 and 68k. Both are CISC, encodings are various lengths. I miss the MOVEM instruction - multiple registers can be moved at once to/from memory - it's like a universal adapter for calling conventions. Smile TRAP instruction is like INT. Memory operations can automatically advance the pointer - which made for rather tight loops.


It's been over 20 years since I've played with it, but the demo scene for 68k is still quite active. Some chips will never die it seems: Z80, 6502, 68k, x86, ...

Post 14 May 2018, 21:31
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Joined: 09 Aug 2005
Posts: 2279
Location: Usono (aka, USA)
Try learning Knuth's MMIX.
Post 15 May 2018, 00:58
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Joined: 09 Aug 2005
Posts: 2279
Location: Usono (aka, USA)
Also take a look at SuperH, which seems to be having a resurgence (soon?).
Post 15 May 2018, 21:09
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