Joined: 24 Mar 2012
Location: Russian Federation, Sochi
Good joke, Mino.
Integer & float datas coded differently.
So, for correct interpretation of thour data thou shold use integer instructions for extracting integer operands, or use float instructions for extract float operands.
There are a few ways to represent numbers with fractional parts, the one you were using was single precision.
So, at the 'nmbr' label, or in eax, the bits are stored as binary scientific notation, more or less. The encoding is pretty standard (I think there can be some variations though), but the IEEE standard for single precision looks like this:
depending on what you are using the register for. I think add, imul, etc use two's complement. The AMD/intel instruction manuals should be able to confirm.
Also, I think it is more recommended to use non-FPU registers when available, so performanig math operations on floating point numbers can be achieved with SSE/avx/etc instructions on the xmm/ymm/zmm registers (depending on what you have). I saw you were using eax and dd, so not sure if you have an older 32-bit architecture that only supports mmx.
I think fasm will define single precision or double precision for you, when you supply immediates as you have. Since single precision is a 32-bit format, dd should encode that, dq should encode 64-bit (double precision).
A useful SSE instruction is cvtsi2ss and its variants. These are listed in the AMD docs and lets the processor convert between integers and floating point formats.
Sorry for the lengthy response, but think I convered some of the topics you brought up. I can provide some small usage examples if needed.
@rugxulo: Sorry, in French, we have another name for floats. And translated "literally", that gives a "comma number" (because FR use ',' as comma in float → 0,97 = 0.97).
@donn: Thank's for informations
@ProMiNick: I don't understand very well "my" joke, but thanks also for informations
@CandyMan: It's clearer now, thank you
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