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flat assembler > Non-x86 architectures > FASMARM v1.43 - Cross assembler for ARM CPUs

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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 15871
Location: 162173 Ryugu
Version 1.43 now available:
Quote:
v1.43 2017-Dec-26
  • Fix a code minimisation logic regression
Note that this version assembles against fasm v1.73.01

Thanks to pepe for providing the example code exhibiting the bug.
Post 26 Dec 2017, 00:20
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 15871
Location: 162173 Ryugu
revolution wrote:
Note that this version assembles against fasm v1.73.01
I have update the download package with the bug fix from fasm v1.73.02
WHATSNEW.TXT wrote:
Fixed a bug in the storage of "virtual as" blocks.
Post 26 Dec 2017, 14:14
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Tomasz Grysztar
Assembly Artist


Joined: 16 Jun 2003
Posts: 6873
Location: Kraków, Poland
revolution wrote:
revolution wrote:
Note that this version assembles against fasm v1.73.01
I have update the download package with the bug fix from fasm v1.73.02
Christmas Edition of fasm. Wink
Post 26 Dec 2017, 17:10
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 15871
Location: 162173 Ryugu
fasm CE (Christmas Edition), to go with Windows CE.

And we can then add fasm NT (New Testament), and fasm XP (Xtended Prayers).
Post 27 Dec 2017, 01:44
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hyphz



Joined: 10 Jan 2018
Posts: 6
This is probably a silly newbie question but I'm having trouble with:

Code:
MMIO_BASE = $3f000000 VIDEOCORE_MBOX = MMIO_BASE + $B880 mov r0, VIDEOCORE_MBOX


Which gives an encoding error. I know from the ARM documentation that this is because of restrictions on 32-bit constants in operands resulting from the bits consumed by the opcode.

However, the ARM documentation advises using pseudo-instructions MOV32 or LDR ,= instead, and FASMWARM doesn't seem to support either of these. The alternative is to use MOVW and MOVT, but looking through the FASM documentation there doesn't seem to be an arithmetic operator to get the high or low byte of a constant.

Is there any more elegant way to do this than breaking the constant in half?
Post 10 Jan 2018, 18:39
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 15871
Location: 162173 Ryugu
If you have a later core that can run the instructions MOVW and MOVT then you can use this:
Code:
movw r0,constant and 0xffff movt r0,constant shr 16
fasmarm doesn't support the ARM assembler pseudo instruction, it only supports the ARM CPU instructions. You can simulate the pseudo instructions with macros.
Code:
macro mov32 reg,value { movw reg,(value) and 0xffff movt reg,(value) shr 16 } mov32 r0,constant
Post 10 Jan 2018, 19:52
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hyphz



Joined: 10 Jan 2018
Posts: 6
Thanks very much revolution, that is really helpful.

Are there any good guidelines for using FASM to generate a "kernel" file (actually baremetal program) that will work with the Raspberry Pi QEMU emulator at https://sourceforge.net/projects/rpiqemuwindows/ ? I've tried putting all my code in a "format elf", "section '.init' executable" block but every time I run QEMU running the monitor shows that the PC is set to zero and the code is not loaded there, nor at $8000 where I think it normally would be meant to be.
Post 12 Jan 2018, 15:58
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 15871
Location: 162173 Ryugu
A kernel is just a raw binary file "format binary" and is usually executed at address zero. You will need to setup at least one serial port and send/receive text to/from there.
Post 12 Jan 2018, 17:00
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hyphz



Joined: 10 Jan 2018
Posts: 6
I thought that too, but it doesn't work out that way. The RasPi QEMU takes the kernel file in a command line parameter and says it's in a linux kernel format, which is listed as one of the standard Linux formats. Running with the -kernel parameter giving a FASMWARM .bin file results in the same problem - PC starts at 0, but there is nothing loaded at 0 but junk (e3 a0 00 00 e5 9f 10 04 e5 9f 20 04 e5 9f f0 04 if it matters!)

Here's the fasm file in case it's useful:
Code:
macro mov32 reg, value { movw reg,(value) and $ffff movt reg,(value) shr 16 } macro ret { mov r15, r14 } macro put32 addr, val { mov32 r0, addr mov32 r1, val str r1, [r0] } macro get32 addr, reg { mov32 reg, addr ldr reg, [reg] } macro spin time { mov r2, time @@: sub r2, 1 bne @b } GPFSEL1 = $20200004 GPSET0 = $2020001C GPCLR0 = $20200028 GPPUD = $20200094 GPPUDCLK0 = $20200098 AUX_ENABLES = $20215004 AUX_MU_IO_REG = $20215040 AUX_MU_IER_REG = $20215044 AUX_MU_IIR_REG = $20215048 AUX_MU_LCR_REG = $2021504C AUX_MU_MCR_REG = $20215050 AUX_MU_LSR_REG = $20215054 AUX_MU_MSR_REG = $20215058 AUX_MU_SCRATCH = $2021505C AUX_MU_CNTL_REG = $20215060 AUX_MU_STAT_REG = $20215064 AUX_MU_BAUD_REG = $20215068 format binary code32 put32 AUX_ENABLES, 1 put32 AUX_MU_IER_REG, 0 put32 AUX_MU_CNTL_REG, 0 put32 AUX_MU_LCR_REG,3 put32 AUX_MU_MCR_REG,0 put32 AUX_MU_IER_REG,0 put32 AUX_MU_IIR_REG,$c6 put32 AUX_MU_BAUD_REG,270 get32 GPFSEL1,r2 and r2,not (7 shl 12) orr r2,(2 shl 12) mov32 r0,GPFSEL1 str r2,[r0] put32 GPPUD,0 spin 150 put32 GPPUDCLK0,(1 shl 14) spin 150 put32 GPPUDCLK0,0 put32 AUX_MU_CNTL_REG,2 put32 AUX_MU_IO_REG, $30 stop: b stop
Post 12 Jan 2018, 17:31
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 15871
Location: 162173 Ryugu
I'm pretty sure that QEMU supports kernel files that are raw binary. I've used it in the past for 64-bit ARM stuff and always used raw binary. Indeed the example file I include in the download is raw binary. Maybe your command line needs tweaking? I'm not sure why you see that problem. Maybe you need to enable SemiHosting?
Code:
SemiHosting = 0xf000 SYS_WRITEC = 3 SYS_WRITE0 = 4 ADP_Stopped_ApplicationExit = 0x20026 angel_SWIreason_ReportException = 0x18 processor cpu64_v8 code64 adr x0,stack_base mov sp,x0 adr x1,hello_world bl show_string adr x1,running_at bl show_string adr x0,$$ bl show_hex adr x1,exec_level bl show_string mrs x0,CurrentEL ubfx x0,x0,2,2 bl show_hex movz x1,ADP_Stopped_ApplicationExit and 0xffff movk x1,ADP_Stopped_ApplicationExit and 0xffff shl 16 stp x1,xzr,[sp,-16]! mov x1,sp mov x0,angel_SWIreason_ReportException hlt SemiHosting show_hex: ;x0 = the value clz x2,x0 bic x2,x2,3 lslv x3,x0,x2 sub sp,sp,16 .loop: ror x3,x3,64-4 and x1,x3,0xf cmp x1,9 add x0,x1,'A'-10 add x1,x1,'0' csel x1,x1,x0,ls strb w1,[sp] mov x1,sp mov x0,SYS_WRITEC hlt SemiHosting add x2,x2,4 tbz x2,6,.loop add sp,sp,16 show_crlf: adr x1,crlf show_string: ;x1 = the string mov x0,SYS_WRITE0 hlt SemiHosting ret hello_world: db 'Hello World!',13,10 crlf: db 13,10,0 running_at: db ' Start address: 0x',0 exec_level: db 'Execution level: ',0 align 16 rb 0x20 stack_base:
Post 12 Jan 2018, 17:47
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hyphz



Joined: 10 Jan 2018
Posts: 6
Hmm. I'm running with:

Code:
qemu-system-arm.exe -M versatilepb -kernel uart.bin -cpu arm1176 -serial vc


From reading an article on semihosting I did learn that qemu loads the code at $10000, and sure enough the code is there when raw binary is used. However R15/PC still starts at $0 so the processor hangs in empty ram. With a different version of QEMU, it jumps back and forth between $10000 and $4 but doesn't get to the "stop" label in the program.
Post 12 Jan 2018, 18:32
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hyphz



Joined: 10 Jan 2018
Posts: 6
I did just try your example and ran it with the same command line plus -semihosting but it didn't produce any output anywhere and the PC locked at 10004. Trying to view the content with "x/10i 0x10000" just produced junk because it didn't seem to understand the 64 bit instructions.
Post 12 Jan 2018, 18:39
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 15871
Location: 162173 Ryugu
Here is the command line that worked for me.
Code:
qemu-system-aarch64.exe -nographic -cpu cortex-a57 -semihosting -m 256 -machine integratorcp -trace events=nul,file=nul -kernel "%1"
Post 13 Jan 2018, 01:15
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hyphz



Joined: 10 Jan 2018
Posts: 6
That worked, thanks Smile
Post 13 Jan 2018, 02:09
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