Joined: 16 Jun 2003
Location: Kraków, Poland
The x86 macro sets I made only define instructions valid for a given processor generation or instruction set extension - there is currently no file for a processor generation that would include RDTSCP (the highest ones are p6.inc and x64.inc)
Also, many extensions like VMX, SMX, etc. are going to require separate files as well. This is going to require careful enumeration and separation of all the instruction sets - I'm even considering releasing a complete set of x86 headers as a separate package if the number of files grows too large. And for a separate package I could consider a different approach, where all instruction macros would be defined at once but you could turn instruction sets on/off on the fly. Such macros would be more complex, that's why I did not do it this way in the headers that are included as an examples with fasmg, but if they were released separately it would no longer be a concern.
In current variant yo need to include base instruction set (like 80386.inc, p5.inc, or x64.inc) and all the instruction set extensions, and you need to do it once in the beginning of source. With headers that would have all the instructions but would allow to turn on/off some sets of them, you could enable an extension like AVX only for a selected section of code - this could have some advantages.
Nevertheless, currently my focus is to prepare the headers providing all the necessary tools for writing x86 instruction handlers, like avx512.inc I'm working on, which add macros for parsing AVX-512 syntax and encoding EVEX-based instructions. When I provide such basic macros, it theoretically should be easy for anyone to implement any new/missing instruction handlers based on these facilities. The SCALL example demonstrated how this could be done.
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