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Index > Non-x86 architectures > D-ARM7 Disassembler

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uart777



Joined: 17 Jan 2012
Posts: 369
uart777
D-ARM7 Disassembler

* Free ARMv7 disassembler for X86
* Same format as FASMARM
* Fast & easy to use. No setup or installation. Just drag binary into .EXE and disassembly will appear. Or run .EXE and select file (*.BIN, *.IMG, *.AIF)
* Supports most ARMv7, >5,000+ instructions considering suffixes, way more than other free ARM (v4-5) disassemblers (ARMu, DisARM). (FPA+VFP is unfinished)
* Customizable: Set base address, upper/lowercase, A1-A4+V1-V8, indents, C-style 0x hex constants, pure ASM (remove addresses and code)
* Written according to ARMv7 manual with comments and page # references. See main source: DARM7.INC, 3,700+ lines.

EXAMPLE
Code:
00010000 00000000 dw 0
00010004 E320F000 nop
00010008 E1212374 bkpt 1234h
0001000C E1A01002 mov r1, r2
00010010 E3017234 movw r7, 1234h
00010014 E34A7BCD movt r7, 0ABCDh
00010018 03A0147F moveq r1, 7F000000h
0001001C 11A01312 movne r1, r2, lsl r3
00010020 E0921003 adds r1, r2, r3
00010024 E3821102 orr r1, r2, 80000000h
00010028 C0821413 addgt r1, r2, r3, lsl r4
0001002C E8BD80EF ldmia sp!, {r0-r3,r5-r7,pc}
00010030 E92D40EF stmdb sp!, {r0-r3,r5-r7,lr}
00010034 E05217C3 subs r1, r2, r3, asr 15
00010038 B08213A3 addlt r1, r2, r3, lsr 7
0001003C E83D1A9E ldmda sp!, {r1-r4,r7,r9,r11-r12}
00010040 E9AD08FE stmib sp!, {r1-r7,r11}
00010044 70221413 eorvc r1, r2, r3, lsl r4
00010048 E351087F cmp r1, 7F0000h
0001004C E1D65007 bics r5, r6, r7
00010050 80521473 subshi r1, r2, r3, ror r4
00010054 EA000002 b 10064h
00010058 1A000002 bne 10068h
0001005C 8A000002 bhi 1006Ch
00010060 E0821203 add r1, r2, r3, lsl 4
00010064 E0465007 sub r5, r6, r7
00010068 E0021243 and r1, r2, r3, asr 4
0001006C E1811002 orr r1, r1, r2
00010070 E1C21203 bic r1, r2, r3, lsl 4
00010074 EBFFFFFA bl 10064h
00010078 E12FFF17 bx r7
0001007C E12FFF27 bxj r7
00010080 CAFFFFFA bgt 10070h
00010084 E3A01002 mov r1, 2
00010088 E1A01002 mov r1, r2
0001008C E1B01312 movs r1, r2, lsl r3
00010090 E1E01442 mvn r1, r2, asr 8
00010094 E2821003 add r1, r2, 3
00010098 E0921003 adds r1, r2, r3
0001009C 30A213A3 adclo r1, r2, r3, lsr 7
000100A0 40821413 addmi r1, r2, r3, lsl r4
000100A4 E0421003 sub r1, r2, r3
000100A8 E2521003 subs r1, r2, 3
000100AC E0C21473 sbc r1, r2, r3, ror r4
000100B0 10E21453 rscne r1, r2, r3, asr r4
000100B4 E0021203 and r1, r2, r3, lsl 4
000100B8 E3865007 orr r5, r6, 7
000100BC E19217E3 orrs r1, r2, r3, ror 15
000100C0 E0265007 eor r5, r6, r7
000100C4 B0221413 eorlt r1, r2, r3, lsl r4
000100C8 E1C65007 bic r5, r6, r7
000100CC 81510352 cmphi r1, r2, asr r3
000100D0 E1310002 teq r1, r2
000100D4 E0010392 mul r1, r2, r3
000100D8 E0214392 mla r1, r2, r3, r4
000100DC E0614392 mls r1, r2, r3, r4
000100E0 E0821793 umull r1, r2, r3, r7
000100E4 E0A21793 umlal r1, r2, r3, r7
000100E8 E0421793 umaal r1, r2, r3, r7
000100EC E0C21793 smull r1, r2, r3, r7
000100F0 E0E21793 smlal r1, r2, r3, r7
000100F4 E751F312 smmul r1, r2, r3
000100F8 E7514312 smmla r1, r2, r3, r4
000100FC E75143D2 smmls r1, r2, r3, r4
00010100 E1610382 smulbb r1, r2, r3
00010104 E16103E2 smultt r1, r2, r3
00010108 E16103C2 smulbt r1, r2, r3
0001010C E16103A2 smultb r1, r2, r3
00010110 E1017382 smlabb r1, r2, r3, r7
00010114 E10173E2 smlatt r1, r2, r3, r7
00010118 E10173C2 smlabt r1, r2, r3, r7
0001011C E10173A2 smlatb r1, r2, r3, r7
00010120 E1421783 smlalbb r1, r2, r3, r7
00010124 E14217E3 smlaltt r1, r2, r3, r7
00010128 E14217C3 smlalbt r1, r2, r3, r7
0001012C E14217A3 smlaltb r1, r2, r3, r7
00010130 E7017312 smlad r1, r2, r3
00010134 E7017352 smlsd r1, r2, r3
00010138 E7421713 smlald r1, r2, r3, r7
0001013C E7421753 smlsld r1, r2, r3, r7
00010140 E701F312 smuad r1, r2, r3
00010144 E701F352 smusd r1, r2, r3
00010148 E701F332 smuad r1, r2, r3
0001014C E701F372 smusd r1, r2, r3
00010150 E12103A2 smulwt r1, r2, r3
00010154 E12103E2 smlawt r1, r2, r3
00010158 E1217382 smulwb r1, r2, r3, r7
0001015C E12173C2 smlawb r1, r2, r3, r7
00010160 E8BD80EF ldmia sp!, {r0-r3,r5-r7,pc}
00010164 E92D40EF stmdb sp!, {r0-r3,r5-r7,lr}
00010168 E83D1A9E ldmda sp!, {r1-r4,r7,r9,r11-r12}
0001016C E9AD04FE stmib sp!, {r1-r7,r10}
00010170 E93D00FE ldmdb sp!, {r1-r7}
00010174 E8AD00FE stmia sp!, {r1-r7}
00010178 E9BD00FE ldmib sp!, {r1-r7}
0001017C E82D00FE stmda sp!, {r1-r7}
00010180 E6AF1072 sxtb r1, r2
00010184 E6AF1872 sxtb r1, r2, ror 16
00010188 E6BF1072 sxth r1, r2
0001018C E6BF1872 sxth r1, r2, ror 16
00010190 E68F1072 sxtb16 r1, r2
00010194 E68F1872 sxtb16 r1, r2, ror 16
00010198 E6A21073 sxtab r1, r2, r3
0001019C E6A21873 sxtab r1, r2, r3, ror 16
000101A0 E6B21073 sxtah r1, r2, r3
000101A4 E6B21873 sxtah r1, r2, r3, ror 16
000101A8 E6821073 sxtab16 r1, r2, r3
000101AC E6821873 sxtab16 r1, r2, r3, ror 16
000101B0 E6EF1072 uxtb r1, r2
000101B4 E6EF1872 uxtb r1, r2, ror 16
000101B8 E6FF1072 uxth r1, r2
000101BC E6FF1872 uxth r1, r2, ror 16
000101C0 E6CF1072 uxtb16 r1, r2
000101C4 E6CF1872 uxtb16 r1, r2, ror 16
000101C8 E6E21073 uxtab r1, r2, r3
000101CC E6E21873 uxtab r1, r2, r3, ror 16
000101D0 E6F21073 uxtah r1, r2, r3
000101D4 E6F21873 uxtah r1, r2, r3, ror 16
000101D8 E6C21073 uxtab16 r1, r2, r3
000101DC E6C21873 uxtab16 r1, r2, r3, ror 16
000101E0 E1031052 qadd r1, r2, r3
000101E4 E1231052 qsub r1, r2, r3
000101E8 E1431052 qdadd r1, r2, r3
000101EC E1631052 qdsub r1, r2, r3
000101F0 E6121F93 sadd8 r1, r2, r3
000101F4 E6121F13 sadd16 r1, r2, r3
000101F8 E6121FF3 ssub8 r1, r2, r3
000101FC E6121F73 ssub16 r1, r2, r3
00010200 E6521F93 uadd8 r1, r2, r3
00010204 E6521F13 uadd16 r1, r2, r3
00010208 E6521FF3 usub8 r1, r2, r3
0001020C E6521F73 usub16 r1, r2, r3
00010210 E6321F93 shadd8 r1, r2, r3
00010214 E6321F13 shadd16 r1, r2, r3
00010218 E6321FF3 shsub8 r1, r2, r3
0001021C E6321F73 shsub16 r1, r2, r3
00010220 E6721F93 uhadd8 r1, r2, r3
00010224 E6721F13 uhadd16 r1, r2, r3
00010228 E6721FF3 uhsub8 r1, r2, r3
0001022C E6721F73 uhsub16 r1, r2, r3
00010230 E6121F33 sasx r1, r2, r3
00010234 E6121F53 ssax r1, r2, r3
00010238 E6521F33 uasx r1, r2, r3
0001023C E6521F53 usax r1, r2, r3
00010240 E6321F33 shasx r1, r2, r3
00010244 E6321F53 shsax r1, r2, r3
00010248 E6721F33 uhasx r1, r2, r3
0001024C E6721F53 uhsax r1, r2, r3
00010250 E6221F33 qasx r1, r2, r3
00010254 E6221F53 qsax r1, r2, r3
00010258 E6621F33 uqasx r1, r2, r3
0001025C E6621F53 uqsax r1, r2, r3
00010260 E6221F93 qadd8 r1, r2, r3
00010264 E6221F13 qadd16 r1, r2, r3
00010268 E6221FF3 qsub8 r1, r2, r3
0001026C E6221F73 qsub16 r1, r2, r3
00010270 E6621F93 uqadd8 r1, r2, r3
00010274 E6621F13 uqadd16 r1, r2, r3
00010278 E6621FF3 uqsub8 r1, r2, r3
0001027C E6621F73 uqsub16 r1, r2, r3
00010280 E6A61012 ssat r1, 7, r2
00010284 E6A61012 ssat r1, 7, r2
00010288 E6A61052 ssat r1, 7, r2, asr 32
0001028C E6A61612 ssat r1, 7, r2, lsl 12
00010290 E6EF1012 usat r1, 15, r2
00010294 E6EF1452 usat r1, 15, r2, asr 8
00010298 E6A61F32 ssat16 r1, 7, r2
0001029C E6E71F32 usat16 r1, 7, r2
000102A0 E781F312 usad8 r1, r2, r3
000102A4 E7817312 usada8 r1, r2, r3, r7
000102A8 E5921000 ldr r1, [r2]
000102AC E5B21004 ldr r1, [r2, 4]!
000102B0 E5921008 ldr r1, [r2, 8]
000102B4 E5921123 ldr r1, [r2, 123h]
000102B8 E59F1123 ldr r1, [pc, 123h]
000102BC E5121123 ldr r1, [r2, -123h]
000102C0 E51F1123 ldr r1, [pc, -123h]
000102C4 E7921003 ldr r1, [r2, r3]
000102C8 E7B21003 ldr r1, [r2, r3]!
000102CC E7921203 ldr r1, [r2, r3, lsl 4]
000102D0 E7921463 ldr r1, [r2, r3, ror 8]
000102D4 E7121003 ldr r1, [r2, -r3]
000102D8 E4921008 ldr r1, [r2], 8
000102DC E4121008 ldr r1, [r2], -8
000102E0 E6921003 ldr r1, [r2], r3
000102E4 E6121003 ldr r1, [r2], -r3
000102E8 E5821000 str r1, [r2]
000102EC E5A21004 str r1, [r2, 4]!
000102F0 E5821008 str r1, [r2, 8]
000102F4 E5821123 str r1, [r2, 123h]
000102F8 E58F1123 str r1, [pc, 123h]
000102FC E5021123 str r1, [r2, -123h]
00010300 E50F1123 str r1, [pc, -123h]
00010304 E7821003 str r1, [r2, r3]
00010308 E7A21003 str r1, [r2, r3]!
0001030C E7821203 str r1, [r2, r3, lsl 4]
00010310 E7821463 str r1, [r2, r3, ror 8]
00010314 E7021003 str r1, [r2, -r3]
00010318 E4821008 str r1, [r2], 8
0001031C E4021008 str r1, [r2], -8
00010320 E6821003 str r1, [r2], r3
00010324 E6021003 str r1, [r2], -r3
00010328 E5D21000 ldrb r1, [r2]
0001032C E5F21004 ldrb r1, [r2, 4]!
00010330 E5D21008 ldrb r1, [r2, 8]
00010334 E5D21123 ldrb r1, [r2, 123h]
00010338 E5DF1123 ldrb r1, [pc, 123h]
0001033C E5521123 ldrb r1, [r2, -123h]
00010340 E55F1123 ldrb r1, [pc, -123h]
00010344 E7D21003 ldrb r1, [r2, r3]
00010348 E7F21003 ldrb r1, [r2, r3]!
0001034C E7D21203 ldrb r1, [r2, r3, lsl 4]
00010350 E7D21463 ldrb r1, [r2, r3, ror 8]
00010354 E7521003 ldrb r1, [r2, -r3]
00010358 E4D21008 ldrb r1, [r2], 8
0001035C E4521008 ldrb r1, [r2], -8
00010360 E6D21003 ldrb r1, [r2], r3
00010364 E6521003 ldrb r1, [r2], -r3
00010368 E5C21000 strb r1, [r2]
0001036C E5E21004 strb r1, [r2, 4]!
00010370 E5C21008 strb r1, [r2, 8]
00010374 E5C21123 strb r1, [r2, 123h]
00010378 E5CF1123 strb r1, [pc, 123h]
0001037C E5421123 strb r1, [r2, -123h]
00010380 E54F1123 strb r1, [pc, -123h]
00010384 E7C21003 strb r1, [r2, r3]
00010388 E7E21003 strb r1, [r2, r3]!
0001038C E7C21203 strb r1, [r2, r3, lsl 4]
00010390 E7C21463 strb r1, [r2, r3, ror 8]
00010394 E7421003 strb r1, [r2, -r3]
00010398 E4C21008 strb r1, [r2], 8
0001039C E4421008 strb r1, [r2], -8
000103A0 E6C21003 strb r1, [r2], r3
000103A4 E6421003 strb r1, [r2], -r3
000103A8 E1D210B0 ldrh r1, [r2]
000103AC E1D210B8 ldrh r1, [r2, 8]
000103B0 E1F217BF ldrh r1, [r2, 7Fh]!
000103B4 E15217BF ldrh r1, [r2, -7Fh]
000103B8 E19210B3 ldrh r1, [r2, r3]
000103BC E13210B3 ldrh r1, [r2, -r3]!
000103C0 E0D212B0 ldrh r1, [r2], 20h
000103C4 E09210B3 ldrh r1, [r2], r3
000103C8 E05210B8 ldrh r1, [r2], -8
000103CC E01210B3 ldrh r1, [r2], -r3
000103D0 E1D210D0 ldrsb r1, [r2]
000103D4 E1D210D8 ldrsb r1, [r2, 8]
000103D8 E1F217DF ldrsb r1, [r2, 7Fh]!
000103DC E15217DF ldrsb r1, [r2, -7Fh]
000103E0 E19210D3 ldrsb r1, [r2, r3]
000103E4 E13210D3 ldrsb r1, [r2, -r3]!
000103E8 E0D212D0 ldrsb r1, [r2], 20h
000103EC E09210D3 ldrsb r1, [r2], r3
000103F0 E05210D8 ldrsb r1, [r2], -8
000103F4 E01210D3 ldrsb r1, [r2], -r3
000103F8 E1D210F0 ldrsh r1, [r2]
000103FC E1D210F8 ldrsh r1, [r2, 8]
00010400 E1F217FF ldrsh r1, [r2, 7Fh]!
00010404 E15217FF ldrsh r1, [r2, -7Fh]
00010408 E19210F3 ldrsh r1, [r2, r3]
0001040C E13210F3 ldrsh r1, [r2, -r3]!
00010410 E0D212F0 ldrsh r1, [r2], 20h
00010414 E09210F3 ldrsh r1, [r2], r3
00010418 E05210F8 ldrsh r1, [r2], -8
0001041C E01210F3 ldrsh r1, [r2], -r3
00010420 E1C420D0 ldrd r2, [r4]
00010424 E1C420D8 ldrd r2, [r4, 8]
00010428 E1E427DF ldrd r2, [r4, 7Fh]!
0001042C E14427DF ldrd r2, [r4, -7Fh]
00010430 E18420D5 ldrd r2, [r4, r5]
00010434 E12420D5 ldrd r2, [r4, -r5]!
00010438 E0C422D0 ldrd r2, [r4], 20h
0001043C E08420D5 ldrd r2, [r4], r5
00010440 E04420D8 ldrd r2, [r4], -8
00010444 E00420D5 ldrd r2, [r4], -r5
00010448 E1C210B0 strh r1, [r2]
0001044C E1C210B8 strh r1, [r2, 8]
00010450 E1E217BF strh r1, [r2, 7Fh]!
00010454 E14217BF strh r1, [r2, -7Fh]
00010458 E18210B3 strh r1, [r2, r3]
0001045C E12210B3 strh r1, [r2, -r3]!
00010460 E0C212B0 strh r1, [r2], 20h
00010464 E08210B3 strh r1, [r2], r3
00010468 E04210B8 strh r1, [r2], -8
0001046C E00210B3 strh r1, [r2], -r3
00010470 E1C420F0 strd r2, [r4]
00010474 E1C420F8 strd r2, [r4, 8]
00010478 E1E427FF strd r2, [r4, 7Fh]!
0001047C E14427FF strd r2, [r4, -7Fh]
00010480 E18420F5 strd r2, [r4, r5]
00010484 E12420F5 strd r2, [r4, -r5]!
00010488 E0C422F0 strd r2, [r4], 20h
0001048C E08420F5 strd r2, [r4], r5
00010490 E04420F8 strd r2, [r4], -8
00010494 E00420F5 strd r2, [r4], -r5
00010498 E6821013 pkhbt r1, r2, r3
0001049C E6821393 pkhbt r1, r2, r3, lsl 7
000104A0 E68213D3 pkhbt r1, r2, r3, asr 7
000104A4 E16F3F15 clz r3, r5
000104A8 E7C91192 bfi r1, r2, 3, 7
000104AC E7CB2213 bfi r2, r3, 4, 8
000104B0 E7C4111F bfc r1, 2, 3
000104B4 E7A611D2 sbfx r1, r2, 3, 7
000104B8 E7E611D2 ubfx r1, r2, 3, 7
000104BC E6BF5F37 rev r5, r7
000104C0 E6BF5FB7 rev16 r5, r7
000104C4 E6FF5FB7 revsh r5, r7
000104C8 E6FF5F37 rbit r5, r7
000104CC E320F000 nop
000104D0 00000000 dw 0
000104D4 00000001 dw 1
000104D8 E1212374 bkpt 1234h
000104DC E320F0F7 dbg 7
000104E0 EF001234 svc 1234h
000104E4 E1600072 smc 2
000104E8 F8ED0510 srs sp!, 10h
000104EC F57FF05B dmb ish
000104F0 F57FF047 dsb nsh
000104F4 F57FF06F isb sy
000104F8 F5D1F000 pld [r1]
000104FC F591F000 pldw [r1]
00010500 E1081097 swp r1, r7, [r8]
00010504 E1481097 swpb r1, r7, [r8]
00010508 E320F004 sev 
0001050C F1010000 setend le
00010510 F1010200 setend be
00010514 F8970A00 rfe r7
00010518 E320F002 wfe 
0001051C E320F003 wfi 
00010520 E320F001 yield 
00010524 E10F7000 mrs r7, CPSR
00010528 E14F7000 mrs r7, SPSR
0001052C E128F005 msr CPSR_f, r5
00010530 E124F005 msr CPSR_s, r5
00010534 E122F005 msr CPSR_x, r5
00010538 E121F005 msr CPSR_c, r5
0001053C E12CF005 msr CPSR_fs, r5
00010540 E12FF005 msr CPSR_fsxc, r5
00010544 E168F005 msr SPSR_f, r5
00010548 E164F005 msr SPSR_s, r5
0001054C E162F005 msr SPSR_x, r5
00010550 E161F005 msr SPSR_c, r5
00010554 E16CF005 msr SPSR_fs, r5
00010558 E16FF005 msr SPSR_fsxc, r5
0001055C F1020001 cps 1
00010560 EF001234 svc 1234h
00010564 ED932100 ldc p1, c2, [r3]
00010568 ED843200 stc p2, c3, [r4]
0001056C EDD32100 ldcl p1, c2, [r3]
00010570 EDC43200 stcl p2, c3, [r4]
00010574 EC421007 mar acc7, r1, r2
00010578 EC521007 mra r1, r2, acc7
0001057C EEA65117 mcr p1, 5, r5, c6, c7
00010580 EEC21213 mcr p2, 6, r1, c2, c3
00010584 EEE543F6 mcr p3, 7, r4, c5, c6, 7
00010588 EEB65117 mrc p1, 5, r5, c6, c7
0001058C EED21213 mrc p2, 6, r1, c2, c3
00010590 EEF65357 mrc p3, 7, r5, c6, c7, 2
00010594 EC415141 mcrr p1, 4, r5, r1, c1
00010598 EC426232 mcrr p2, 3, r6, r2, c2
0001059C EC537321 mrrc p3, 2, r7, r3, c1
000105A0 EC548412 mrrc p4, 1, r8, r4, c2
000105A4 EE332104 cdp p1, 3, c2, c3, c4
000105A8 EE2322E4 cdp p2, 2, c2, c3, c4, 7
000105AC EE1323E4 cdp p3, 1, c2, c3, c4, 7    
Custom Settings: Uppercase, A1-A4+V1-V8, base=10000h, tight, indent=8, C-style hex, machine code removed:
Code:
00010000 ADDS     A1,A2,A3,LSL 7
00010004 SUBSHI   V1,V2,V3
00010008 ADCLO    SP,V6,V7,ASR V8
0001000C LDMIA    SP!,{A1-A4,V2-V5,PC}
00010010 STMDB    SP!,{A1-A4,V2-V5,LR}
00010014 LDR      A1,[V1,V2,LSL 16]!
00010018 CMP      V1,0x80000000
0001001C RSCMI    V3,V3,A4,ROR 7    
USAGE

1. Fastest way: Drag+drop file into DARM7.EXE
2. Open DARM7.EXE and select file (Duh)
3. Use command line, *.BAT or shell execute.
Code:
; darm7 file.bin
; darm7 file.bin [options...]

darm7 file.bin asm base=10000h
darm7 file.bin asm case av 0x indent=8

; Options:

case           - Set uppercase. Default lowercase
base=10000h    - Set begin address. Default=0
start=200h     - Start disassembly at offset
end=700h       - Disassemble until offset
size=500h      - Or # bytes (end-start)
view=200h      - Advance to offset in viewer
asm            - Pure ASM. No addresses or code
                 which is default
silent         - Just save .TXT file. Don't
                 open after
av             - View registers A1-A4+V1-V8
                 instead of R0-R11?
0x             - Use C-style hex numbers? 0xAB.
                 Default: 7Fh. 0 prefix if needed
indent=10      - Indent operands by # spaces.
                 Default: 0/NO. Try 8/10/12/14
tight          - No space after operands/commas.
                 Default is space after
compact        - Compact form for "DP A, A, B"?
                 Default: No
literal        - Display & for PC relative LDR?
shift          - View shifts instead of mov+shift?
pseudo         - Enable pseudo instructions?
                 Disabled by default
html           - Output HTML file with syntax
                 highlighting then open    
Source Preview
Code:
; $$$$$$$$$$$$$ D-ARM7 DISASSEMBLER $$$$$$$$$$$$$$
; *************** STAR^2 SOFTWARE ****************
; ?????????????????? DARM7.INC ???????????????????
;               ___               ____
;              / _ \___ _______ _/_  /
;             / // / _ `/ __/  ' \/ /
;            /____/\_,_/_/ /_/_/_/_/

;          D-ARM7 Disassembler Lite/Beta...

;;;;;;;;;;;;;;;;;;; CONDITIONS ;;;;;;;;;;;;;;;;;;;

numeric C.*,\
 EQ, NE, HS, LO, MI, PL, VS, VC,\
 HI, LS, GE, LT, GT, LE, AL, NV

texts conditions.ta[]=\
 'eq', 'ne', 'hs', 'lo', 'mi', 'pl', 'vs', 'vc',\
 'hi', 'ls', 'ge', 'lt', 'gt', 'le', 'al', 'nv'

;;;;;;;;;;;;;;;;;;; REGISTERS ;;;;;;;;;;;;;;;;;;;;

numeric R.*,\             ; R.0-R.15
 0, 1, 2, 3, 4, 5, 6, 7,\
 8, 9, 10, 11, 12, 13, 14, 15

texts registers.ta[]=\
 'r0', 'r1', 'r2', 'r3', 'r4', 'r5', 'r6', 'r7',\
 'r8', 'r9', 'r10', 'r11', 'r12', 'sp', 'lr', 'pc'

texts registers2.ta[]=\
 'a1', 'a2', 'a3', 'a4', 'v1', 'v2', 'v3', 'v4',\
 'v5', 'v6', 'v7', 'v8', 'vx', 'sp', 'lr', 'pc'

texts registers3.ta[]='r12', 'r13', 'r14', 'r15'

;;;;;;;;;;;;;;;;; INSTRUCTIONS ;;;;;;;;;;;;;;;;;;;

; ids and names. 370+ instructions (or 7,000+
; considering suffixes/variations and that's
; a low estimate)

; ? CCCC condition, leftmost 4 BITs #28-#31
; $ C+S BIT. s/et flags?
; . C+precision (FPA)
; % C+precision+rounding (FPA)

; FPA: precision: s=single, d=double,
; e=extended, p=packed BCD (only valid
; for ldf/stf). round: p=+infinity,
; m=-infinity. z=zero

text c.t='?', cs.t='$', p.t='.',\
 f.t='%', s.t='s', v.t='^'

messages i.names.ta,\
 I.UNKNOWN='?',\
 I.DATA='dw', I.UNDEFINED='(?)',\
 I.ABS='abs%', I.ACS='acs%', I.ADC='adc$',\
 I.ADD='add$', I.ADF='adf%', I.ADR='adr?',\
 I.AND='and$', I.ASN='asn%', I.ASR='asr$',\
 I.ATN='atn%', I.B='b?', I.BFC='bfc?',\
 I.BFI='bfi?', I.BIC='bic$', I.BKPT='bkpt?',\
 I.BL='bl?', I.BLX='blx?', I.BX='bx?',\
 I.BXJ='bxj?', I.CDP='cdp', I.CDP2='cdp2',\
 I.CLREX='clrex', I.CLZ='clz?', I.CMN='cmn$',\
 I.CMF='cmf?', I.CMP='cmp$', I.CNF='cnf?',\
 I.COS='cos%', I.CPS='cps', I.DBG='dbg?',\
 I.DMB='dmb', I.DSB='dsb', I.DVF='dvf%',\
 I.EOR='eor$', I.EXP='exp%', I.FDV='fdv%',\
 I.FIX='fix%', I.FLT='flt%', I.FML='fml%',\
 I.FRD='frd%', I.ISB='isb?', I.LDC='ldc?',\
 I.LDC2='ldc2', I.LDCL='ldcl?',\
 I.LDC2L='ldc2l', I.LDF='ldf.',\
 I.LDMDB='ldmdb?', I.LDMIB='ldmib?',\
 I.LDMDA='ldmda?', I.LDMIA='ldmia?',\
 I.LDR='ldr?', I.LDRB='ldrb?',\
 I.LDRBT='ldrbt?', I.LDRD='ldrd?',\
 I.LDREX='ldrex?', I.LDREXB='ldrexb?',\
 I.LDREXD='ldrexd?', I.LDREXH='ldrexh?',\
 I.LDRH='ldrh?', I.LDRHT='ldrht?',\
 I.LDRSB='ldrsb?', I.LDRSBT='ldrsbt?',\
 I.LDRSH='ldrsh?', I.LDRSHT='ldrsht?',\
 I.LDRT='ldrt?', I.LFMEA='lfmea?',\
 I.LFMED='lfmed?', I.LFMFA='lfmfa?',\
 I.LFMFD='lfmfd?', I.LGN='lgn%', I.LOG='log%',\
 I.LSL='lsl$', I.LSR='lsr$', I.MAR='mar?',\
 I.MCR='mcr?', I.MCR2='mcr2', I.MCRR='mcrr?',\
 I.MCRR2='mcrr2', I.MLA='mla$', I.MLS='mls$',\
 I.MNF='mnf%', I.MOV='mov$', I.MOVT='movt?',\
 I.MOVW='movw?', I.MRA='mra?', I.MRC='mrc?',\
 I.MRC2='mrc2', I.MRRC='mrrc?',\
 I.MRRC2='mrrc2', I.MRS='mrs?', I.MSR='msr?',\
 I.MUF='muf%', I.MUL='mul$', I.MULL='mull$',\
 I.MVF='mvf%', I.MVN='mvn$', I.NOP='nop',\
 I.NRM='nrm%', I.ORR='orr$', I.PKHBT='pkhbt?',\
 I.PKHTB='pkhtb?', I.PLD='pld', I.PLDW='pldw',\
 I.PLI='pli', I.POL='pol%', I.POW='pow%',\
 I.QADD='qadd?', I.QADD16='qadd16?',\
 I.QADD8='qadd8?', I.QASX='qasx?',\
 I.QDADD='qdadd?', I.QDSUB='qdsub?',\
 I.QSAX='qsax?', I.QSUB='qsub?',\
 I.QSUB16='qsub16?', I.QSUB8='qsub8?',\
 I.RBIT='rbit?', I.RDF='rdf%', I.REV='rev?',\
 I.REV16='rev16?', I.REVSH='revsh?',\
 I.RFC='rfc?', I.RFE='rfe', I.RFS='rfs?',\
 I.RMF='rmf%', I.RND='rnd%', I.ROR='ror$',\
 I.RPW='rpw%', I.RRX='rrx?', I.RSB='rsb$',\
 I.RSC='rsc$', I.RSF='rsf%', I.SADD16='sadd16?',\
 I.SADD8='sadd8?', I.SASX='sasx?', I.SBC='sbc$',\
 I.SBFX='sbfx?', I.SDIV='sdiv?',\
 I.SEL='sel?', I.SETEND='setend', I.SEV='sev?',\
 I.SFMEA='sfmea?', I.SFMED='sfmed?',\
 I.SFMFA='sfmfa?', I.SFMFD='sfmfd?',\
 I.SHADD16='shadd16?', I.SHADD8='shadd8?',\
 I.SHASX='shasx?', I.SHSAX='shsax?',\
 I.SHSUB16='shsub16?', I.SHSUB8='shsub8?',\
 I.SIN='sin%', I.SMC='smc?',\
 I.SMLABB='smlabb?', I.SMLABT='smlabt?',\
 I.SMLAD='smlad?', I.SMLAL='smlal$',\
 I.SMLALBB='smlalbb?', I.SMLALBT='smlalbt?',\
 I.SMLALD='smlald?', I.SMLALTB='smlaltb?',\
 I.SMLALTT='smlaltt?', I.SMLATB='smlatb?',\
 I.SMLATT='smlatt?', I.SMLAWB='smlawb?',\
 I.SMLAWT='smlawt?', I.SMLSD='smlsd?',\
 I.SMLSLD='smlsld?', I.SMMLA='smmla?',\
 I.SMMLS='smmls?', I.SMMUL='smmul?',\
 I.SMUAD='smuad?', I.SMUADX='smuadx?',\
 I.SMULBB='smulbb?', I.SMULBT='smulbt?',\
 I.SMULL='smull$', I.SMULTB='smultb?',\
 I.SMULTT='smultt?', I.SMULWB='smulwb?',\
 I.SMULWT='smulwt?', I.SMUSD='smusd?',\
 I.SMUSDX='smusdx?', I.SQT='sqt%', I.SRS='srs',\
 I.SSAT='ssat?', I.SSAT16='ssat16?',\
 I.SSAX='ssax?', I.SSUB8='ssub8?',\
 I.SSUB16='ssub16?', I.STC='stc?',\
 I.STC2='stc2', I.STCL='stcl?',\
 I.STC2L='stc2l', I.STF='stf.',\
 I.STMIA='stmia?', I.STMDA='stmda?',\
 I.STMIB='stmib?', I.STMDB='stmdb?',\
 I.STR='str?', I.STRB='strb?', I.STRBT='strbt?',\
 I.STRD='strd?', I.STREX='strex?',\
 I.STREXB='strexb?', I.STREXD='strexd?',\
 I.STREXH='strexh?', I.STRH='strh?',\
 I.STRHT='strht?', I.STRT='strt?',\
 I.SUB='sub$', I.SUF='suf%', I.SVC='svc?',\
 I.SWP='swp?', I.SWPB='swpb?',\
 I.SXTAB='sxtab?', I.SXTAH='sxtah?',\
 I.SXTAB16='sxtab16?', I.SXTB='sxtb?',\
 I.SXTB16='sxtb16?', I.SXTH='sxth?',\
 I.TAN='tan%', I.TEQ='teq$', I.TST='tst$',\
 I.UADD16='uadd16?', I.UADD8='uadd8?',\
 I.UASX='uasx?', I.UBFX='ubfx?', I.UDIV='udiv?',\
 I.UHADD16='uhadd16?', I.UHADD8='uhadd8?',\
 I.UHASX='uhasx?', I.UHSAX='uhsax?',\
 I.UHSUB16='uhsub16?', I.UHSUB8='uhsub8?',\
 I.UMAAL='umaal$', I.UMLAL='umlal$',\
 I.UMULL='umull$', I.UQADD16='uqadd16?',\
 I.UQADD8='uqadd8?', I.UQASX='uqasx?',\
 I.UQSAX='uqsax?', I.UQSUB16='uqsub16?',\
 I.UQSUB8='uqsub8?', I.URD='urd%',\
 I.USAD8='usad8?', I.USADA8='usada8?',\
 I.USAT='usat?', I.USAT16='usat16?',\
 I.USAX='usax?', I.USUB16='usub16?',\
 I.USUB8='usub8?', I.UXTAB='uxtab?',\
 I.UXTAB16='uxtab16?', I.UXTAH='uxtah?',\
 I.UXTB='uxtb?', I.UXTB16='uxtb16?',\
 I.UXTH='uxth?', I.VABA='vaba',\
 I.VABAL='vabal', I.VABD='vabd',\
 I.VABDL='vabdl', I.VABS='vabs',\
 I.VACGE='vacge', I.VACGT='vacgt',\
 I.VACLE='vacle', I.VACLT='vaclt',\
 I.VADD='vadd', I.VADDHN='vaddhn',\
 I.VADDL='vaddl', I.VADDW='vaddw',\
 I.VAND='vand', I.VBIC='vbic', I.VBIF='vbif',\
 I.VBIT='vbit', I.VBSL='vbsl', I.VCEQ='vceq',\
 I.VCGE='vcge', I.VCGT='vcgt', I.VCLE='vcle',\
 I.VCLS='vcls', I.VCLT='vclt', I.VCLZ='vclz',\
 I.VCMP='vcmp', I.VCMPE='vcmpe', I.VCNT='vcnt',\
 I.VCVT='vcvt', I.VCVTB='vcvtb',\
 I.VCVTR='vcvtr', I.VCVTT='vcvtt',\
 I.VDIV='vdiv', I.VDUP='vdup', I.VEOR='veor',\
 I.VEXT='vext', I.VFMA='vfma', I.VFMS='vfms',\
 I.VFNMA='vfnma', I.VFNMS='vfnms',\
 I.VHADD='vhadd', I.VHSUB='vhsub', I.VLD1='vld1',\
 I.VLD2='vld2', I.VLD3='vld3', I.VLD4='vld4',\
 I.VLDMIA='vldmia', I.VLDMDB='vldmdb',\
 I.VLDR='vldr', I.VMAX='vmax', I.VMIN='vmin',\
 I.VMLA='vmla', I.VMLAL='vmlal',\
 I.VMLS='vmls', I.VMLSL='vmlsl', I.VMOV='vmov',\
 I.VMOVL='vmovl', I.VMOVN='vmovn', I.VMRS='vmrs',\
 I.VMSR='vmsr', I.VMUL='vmul', I.VMULL='vmull',\
 I.VMVN='vmvn', I.VNEG='vneg', I.VNMLA='vnmla',\
 I.VNMLS='vnmls', I.VNMUL='vnmul',\
 I.VORR='vorr', I.VORN='vorn', I.VPADAL='vpadal',\
 I.VPADD='vpadd', I.VPADDL='vpaddl',\
 I.VPMAX='vpmax', I.VPMIN='vpmin', I.VPOP='vpop',\
 I.VPUSH='vpush', I.VQABS='vqabs',\
 I.VQADD='vqadd', I.VQDMLAL='vqdmlal',\
 I.VQDMLSL='vqdmlsl', I.VQDMULH='vqdmulh',\
 I.VQDMULL='vqdmull', I.VQMOVN='vqmovn',\
 I.VQMOVUN='vqmovun', I.VQRDMULH='vqrdmulh',\
 I.VQRSHL='vqrshl', I.VQRSHRN='vqrshrn',\
 I.VQRSHRUN='vqrshrun', I.VQNEG='vqneg',\
 I.VQSHL='vqshl', I.VQSHLU='vqshlu',\
 I.VQSHRN='vqshrn', I.VQSHRUN='vqshrun',\
 I.VQSUB='vqsub', I.VRADDHN='vraddhn',\
 I.VRECPE='vrecpe', I.VRECPS='vrecps',\
 I.VREV16='vrev16', I.VREV32='vrev32',\
 I.VREV64='vrev64', I.VRHADD='vrhadd',\
 I.VRSHL='vrshl', I.VRSHR='vrshr',\
 I.VRSHRN='vrshrn', I.VRSRA='vrsra',\
 I.VRSQRTE='vrsqrte', I.VRSQRTS='vrsqrts',\
 I.VRSUBHN='vrsubhn', I.VSHL='vshl',\
 I.VSHLL='vshll', I.VSHR='vshr',\
 I.VSHRN='vshrn', I.VSLI='vsli',\
 I.VSQRT='vsqrt', I.VSRA='vsra', I.VSRI='vsri',\
 I.VST1='vst1', I.VST2='vst2', I.VST3='vst3',\
 I.VST4='vst4', I.VSTMIA='vstmia',\
 I.VSTMDB='vstmdb', I.VSTR='vstr',\
 I.VSUB='vsub', I.VSUBHN='vsubhn',\
 I.VSUBL='vsubl', I.VSUBW='vsubw', I.VSWP='vswp',\
 I.VTBL='vtbl', I.VTBX='vtbx', I.VTRN='vtrn',\
 I.VTST='vtst', I.VUZP='vuzp', I.VZIP='vzip',\
 I.WFC='wfc?', I.WFE='wfe?', I.WFI='wfi?',\
 I.WFS='wfs?', I.YIELD='yield?'    
Code:
 .if.bits 27-25=011b      ; #227, A5-16.
   .if.bit 4              ; media
     jmp .mi              ; instructions
   .end
 .end
 .if.bits 31-27=11110b    ; A5.7.1
   jmp .misc2             ; miscellaneous 2
 .end
 .if.bits 27-26=10b       ; branch
   .if.bit 25
     .if.bit 24           ; with link?
       return I.BL
     .end
     return I.B
   .end                   ; block data
   jmp .bdt               ; transfer
 .end
 .if.not.bit 25           ; #210, A5-2
   .if.bits 27-26=0       ; class 0
     let op=i,\
      op>>>20, op&11001b  ; op=not 10xx0
     .if op<>10000b
       .if.not.bit 4      ; op=xxx0. data
         jmp .dpr         ; processing register
       .end
       .if.not.bit 7      ; op=0xx1. data
         jmp .dprsr       ; processing register
       .end               ; shifted register
     .end
   .end
   .if.bits 24-23=10b
     .if.not.bit 20
       .if.not.bit 7      ; miscellaneous
         jmp .misc
       .end
       .if.not.bit 4      ; multiply half
         jmp .mulh
       .end
     .end
   .end
   .if.bits 7-4=1001b
     .if.not.bit 24       ; multiply
       jmp .mula          ; accumulate
     .end
     jmp .sync            ; synchronization
   .end
   .if.not.bit 24         ; op=0xx1x
     .if.bit 21
       .if.bits 7-4=1011b ; load/store extra
         jmp .lsu         ; unprivileged
       .end
       .if.bits 7-6=11b
         .if.bit 4
           jmp .lsu
         .end
       .end
     .end
   .end
   jmp .ldst              ; load/store
 .else                    ; op=1
   let op=i,\             ; data processing
    op>>>20, op&11111b    ; move 16BIT
   .if op=10000b          ; immediate
     return I.MOVW
   .end
   .if op=10100b
     return I.MOVT
   .end
   .if.bits 24-23=10b     ; msr immediate
     .if.bits 21-20=10b   ; and hints
       jmp .msrih
     .end
   .end
   .if.bit 25             ; not 10xx0
     .if.not.bit 26
       jmp .dpi           ; data processing
     .end                 ; immediate
   .end
 .end         

 ; #218, A5.2.5, A5-7 - multiply accumulate

 .mula:
 let op=i,\
  op>>>21, op&111b
 .if op=0
   return I.MUL           ; 000x
 .else.if op=1
   return I.MLA           ; 001x
 .end
 let op=i,\               ; 23-20
  op>>>20, op&1111b
 .if op=0100b
   return I.UMAAL
 .else.if op=0101b
   return I.UNDEFINED
 .else.if op=0110b
   return I.MLS
 .else.if op=0111b
   return I.UNDEFINED
 .end
 let op=i,\
  op>>>21, op&111b
 .if op=100b
   return I.UMULL
 .else.if op=101b
   return I.UMLAL
 .else.if op=110b
   return I.SMULL
 .else.if op=111b
   return I.SMLAL
 .end
 return I.UNKNOWN

 ; #232, A5.4.4, A5-20 - signed multiplies

 .smul:
 let op=i,\
  op>>>20, op&111b
 .if op=0
   .if.bits 7-6=0
     .if.bits 15-12=1111b
       return I.SMUAD
     .end
     return I.SMLAD
   .end
   .if.bits 7-6=1
     .if.bits 15-12=1111b
       return I.SMUSD
     .end
     return I.SMLSD
   .end
 .else.if op=100b
   .if.bits 7-6=0
     return I.SMLALD
   .end
   .if.bits 7-6=1
     return I.SMLSLD
   .end
 .else.if op=101b
   .if.bits 7-6=0
     .if.bits 15-12=1111b
       return I.SMMUL
     .end
     return I.SMMLA
   .end
   .if.bits 7-6=11b
     return I.SMMLS
   .end
 .end
 return I.UNKNOWN   

 ; #219, A5.2.7, A5-9 - signed multiply half

 .mulh:
 let op=i,\
  op>>>21, op&11b
 .if op=0
   let op=i,\
    op>>>5, op&11b
   .if op=0
     return I.SMLABB
   .else.if op=1
     return I.SMLATB
   .else.if op=2
     return I.SMLABT
   .else.if op=3
     return I.SMLATT
   .end
 .else.if op=1
   let op=i,\
    op>>>5, op&11b
   .if op=0
     return I.SMULWB
   .else.if op=1
     return I.SMULWT
   .else.if op=2
     return I.SMLAWB
   .else.if op=3
     return I.SMLAWT
   .end
 .else.if op=2
   let op=i,\
    op>>>5, op&11b
   .if op=0
     return I.SMLALBB
   .else.if op=1
     return I.SMLALTB
   .else.if op=2
     return I.SMLALBT
   .else.if op=3
     return I.SMLALTT
   .end
 .else                    ; op=3
   let op=i,\
    op>>>5, op&11b
   .if op=0
     return I.SMULBB
   .else.if op=1
     return I.SMULTB
   .else.if op=2
     return I.SMULBT
   .else.if op=3
     return I.SMULTT
   .end
 .end
 return I.UNKNOWN  

 .lsx:
 .if.bits 6-5=01b
   .if.not.bit 22
     .if.bit 20
       return I.LDRH
     .else
       return I.STRH
     .end
   .else
     .if.not.bit 20
       return I.STRH
     .end
     .if.bits 19-16=1111b
       return I.LDRH
     .end
     return I.LDRH
   .end
 .end
 .if.bits 6-5=10b
   .if.not.bit 22
     .if.bit 20
       return I.LDRSB
     .else
       return I.LDRD
     .end
   .else
     .if.not.bit 20
       return I.LDRD
     .end
     .if.bits 19-16=1111b
       return I.LDRD
     .end
     return I.LDRSB
   .end
 .end
 .if.bits 6-5=11b
   .if.not.bit 22
     .if.bit 20
       return I.LDRSH
     .else
       return I.STRD
     .end
   .else
     .if.not.bit 20
       return I.STRD
     .end
     .if.bits 19-16=1111b
       return I.LDRSH
     .end
     return I.LDRSH
   .end
 .end
 return I.UNKNOWN  

 ; #292, A7.4.1 - 3 registers of same length

 .3rs:
 .if.bits 31-25=1111001b
   .if.not.bit 23
     .if.bits 11-8=0
       .if.bit 4
         return I.VQADD
       .end
       return I.VHADD
     .end
     .if.bits 11-8=1
       .if.not.bit 4
         return I.VRHADD
       .end
       let op=i,\
        op>>>20, op&11b
       .if.not.bit 24
         .if op=0
           return I.VAND
         .end
         .if op=1
           return I.VBIC
         .end
         .if op=2
           return I.VORR
         .end
         .if op=3
           return I.VORN
         .end
       .else
         .if op=0
           return I.VEOR
         .end
         .if op=1
           return I.VBSL
         .end
         .if op=2
           return I.VBIT
         .end
         .if op=3
           return I.VBIF
         .end
       .end
     .end
     .if.bits 11-8=0010b  ; A7-9
       .if.not.bit 4
         return I.VHSUB
       .end
       return I.VQSUB
     .end
     .if.bits 11-8=11b
       .if.bit 4
         return I.VCGE
       .end
       return I.VCGT
     .end
     .if.bits 11-8=0100b  ; #293
       .if.bit 4
         return I.VQSHL
       .end
       return I.VSHL
     .end
     .if.bits 11-8=0101b
       .if.bit 4
         return I.VQRSHL
       .end
       return I.VRSHL
     .end
     .if.bits 11-8=0110b
       .if.bit 4
         return I.VMIN
       .end
       return I.VMAX
     .end
   .end                   ; not 23
   .if.bits 11-8=0111b
     .if.not.bit 4
       .if.not.bit 23
         return I.VABD
       .end
       return I.VABDL
     .end
     return I.VABA
   .end
   .if.bits 11-8=1000b    ; #293
     .if.not.bit 4
       .if.not.bit 24
         .if.bits 21-20=0
           .if.not.bit 23
             return I.VADD
           .end
         .end
       .end
     .else
       .if.not.bit 4
         .if.not.bit 24
           return I.VTST
         .end
       .end
       return I.VCEQ
     .end
   .end
   .if.bits 11-8=1001b
     .if.not.bit 4
       .if.not.bit 20
         .if.not.bit 23
           .if.bit 24
             return I.VMLS
           .end
           return I.VMLA
         .end
       .end
     .end
     .if.not.bit 23
       .if.bits 9-8=1
         .if.bit 4
           return I.VMUL
         .end
       .end
     .end
   .end
   .if.bits 11-10=3
     .if.not.bit 8
       .if.bit 23
         return I.VMUL
       .end
     .end
   .end
   .if.bits 11-8=1010b
     .if.bit 6
       .if.not.bit 23
         .if.not.bit 4
           return I.VMLSL
         .end
         return I.VPMIN
       .end
     .end
   .end
   .if.bits 11-8=1011b
     .if.bit 4
       .if.not.bit 24
         return I.VPADD
       .end
     .else
       .if.bit 6
         .if.not.bit 24
           return I.VQDMULH
         .end
       .end
     .end
     .if.bit 24
       return I.VQRDMULH
     .end
   .end
   .if.bits 11-8=1101b      ; A7.4.1
     .if.not.bit 4          ; A7-9
       .if.not.bit 23       ; #294
         .if.not.bit 24
           .if.bits 21-20=0
             return I.VADD
           .end
           return I.VSUB
         .end
         .if.not.bit 20
           return I.VPADD
         .end
         return I.VABD
       .end
     .else                
       .if.not.bit 24    
         .if.not.bit 21
           return I.VMLA
         .end
         return I.VMLS
       .end
       .if.not.bit 21
         return I.VMUL
       .end
     .end
   .end
   .if.bits 11-8=1110b
     .if.not.bit 4
       .if.not.bit 24
         return I.VCEQ
       .end
       .if.not.bit 21
         return I.VCGE
       .end
       return I.VCGT
     .else
       .if.bit 24
         .if.not.bit 21
           return I.VACGE
         .end
         return I.VACGT
       .end
     .end
   .end
   .if.bits 11-8=1111b
     .if.not.bit 4
       .if.not.bit 24
         .if.not.bit 21
           return I.VMAX
         .end
         return I.VMIN
       .end
       .if.not.bit 21
         return I.VPMAX
       .end
       return I.VPMIN
     .end
     .if.not.bit 24
       .if.not.bit 21
         return I.VRECPS
       .end
       return I.VRSQRTS
     .end
   .end
 .end      

 get [s]=search.n \        ; implicit s
  dps.tb, [id], dps.n
 text.ends t, cs.t         ; ends with $
 .if true
   text.n t
   let eax+t, eax--,\      ; remove $
    byte [eax]=0
   .if [i]&100000h         ; set flags?
     .if [s]=0             ; implicit?
       let byte \          ; no, replace
       [eax]='s', eax++    ; $ with s
     .end
     let byte [eax]=0      ; erase $
   .end
   jmp .c
 .end
 text.ends t, c.t          ; ? condition
 .if true
   text.n t
   let eax+t, eax--
   .c:
    let ecx=[condition]
   .if ecx=C.NV            ; never=always
     jmp .al
   .else.if ecx=C.AL       ; always
     .al:
     let byte [eax]=0      ; no suffix
   .else                   ; attach
     text.copy eax,\
     [conditions.ta+ecx*4]
   .end
 .end

 text.copy i.name.t, t     ; write
 output.t t                ; instruction
 output.space              ; name+space

 .if [indent?]
   text.n t
   .if [indent?]>eax
     let ecx=eax,\
      eax=[indent?],\
      eax-ecx, [n]=eax
     .repeat [n]
       output.space
     .endr
   .end
 .end          

 .if [id]=I.B ; branch...
   .br:
   let eax=[i],\
    eax&0FFFFFFh, eax*4, eax+8,\
    eax+[@ip], eax&0FFFFFFh
    output.h eax
    jmp .r
 .else.if [id]=I.BL
   jmp .br
 .else.if [id]=I.BX
   .bx:
   let eax=[i], eax&0Fh
   output.r eax
   jmp .r
 .else.if [id]=I.BXJ
   jmp .bx
 .end

 ; data processing...

 search.n dp.tb,\
  [id], dp.n
 .if true
   get [s]=search.n \     ; 2 operands?
    dp2.tb, [id], dp2.n   ; mov/cmp/etc
   let ecx=[i]
   .if [s]=0
     jmp @f
   .else.if [id]=I.MOV
     jmp @f
   .else.if [id]=I.MVN
     @@:
     let ecx>>12
   .else
     let ecx>>16
   .end
   let ecx&0Fh
   output.r ecx           ; operand 1
   output.cs              ; ", "
   let eax=[i]
   .if.bit 25             ; immediate?
     .if [s]=0            ; implicit?
       let eax=[i],\
        eax>>16, eax&0Fh  ; operand 2
       output.r eax
       output.cs
     .end
     let eax=[i],\
      ecx=eax, ecx&0FFh,\
      [n]=ecx
     .if eax&0F00h        ; constant
       let ecx=eax,\      ; rotation?
        ecx>>8, ecx&0Fh,\
        ecx*2             ; double
        ror [n], cl
     .end
     .if [n]>=-1          ; 0-9 as
       .if [n]<=9         ; decimal
         output.n [n]
         jmp .r
       .end
     .end
     output.h [n]         ; h number
     jmp .r
   .end
   .if [s]=0              ; operand 2
     let eax=[i],\
      eax>>16, eax&0Fh
     output.r eax
     output.cs            ; ", "
   .end
   let eax=[i], eax&0Fh
   output.r eax           ; operand 3
   let eax=[i]
   .if.not.bit 4          ; shift #i
     let \
      eax=[i], eax>>7,\
      eax&11111b, [n]=eax
     .if false            ; #i=0, no
       jmp .r             ; shift. just
     .end                 ; register
     output.cs            ; ", "
     let eax=[i],\
      eax>>5, eax&11b     ; shift
     output.shift eax     ; type
     output.space
     output.n [n]         ; #number
     jmp .r
   .end
   let \                  ; else, shift
    eax=[i], eax>>8,\     ; by register
    eax&0Fh, [n]=eax
   output.cs              ; ", "
   let eax=[i],\
    eax>>5, eax&11b       ; shift
   output.shift eax       ; type
   output.space
   output.r [n]           ; register
   jmp .r                 ; return
 .end                     ; end dp

 ; load/store multiple

 .if.search.table \
   lsm.tb, [id]
   output.rx 16              ; base register
   let eax=[i]
   .if.bit 21                ; write-back?
     output.c '!'
   .end
   output.cs
   output.c '{'
   let [n]=0
   .loop [x]=0 to 16         ; register list
     let eax=1,\
      ecx=[x], eax<<cl
     .if [i]&eax             ; register
       let eax=[x],\
        [first]=eax,\
        eax++, [j]=eax
       .loop [y]=[j] to 16   ; how many?
         let eax=1,\
          ecx=[y],\
          eax<<cl
         .if.n [i]&eax       ; not in list?
           jmp @f
         .end
       .endl
       @@:
       let eax=[y], eax--,\
        [last]=eax
       .if [first]<eax       ; register list?
         output.r [first]
         output.c '-'
         output.r [last]
         let [n]++,\         ; advance
          [x]=[y]            ; outer loop
       .else                 ; just one
         output.r [x]        ; register?
       .end
       .if [n]
         output.c ','
       .end
     .end
     @@:
   .endl
   text.n dasm.t             ; replace
   let eax--,\               ; last ,
    eax+dasm.t,\             ; with }
    byte [eax]='}'
   jmp .r
 .end    

Today is my birthday Smile 3 consecutive 7s: 10-7-77. Promised myself I'd release it before this day. Time: 12-15 hours, average 1-3 hours a day for about a week.


Description:
Download
Filename: d-arm7.zip
Filesize: 88.41 KB
Downloaded: 2030 Time(s)

Post 08 Oct 2013, 03:30
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17641
Location: In your JS exploiting you and your system
revolution
Because many of the coprocessors overlap in the instruction space then it might be prudent to have a coprocessor selection option also.

BTW: The existence of VFP is a lot more common than FPA. So if you only want to support one coprocessor then perhaps VFP+NEON (these two do not overlap) would be a better choice.

Also, what about thumb? Lots of existing code uses it. If you allow for DWARF format then you can use the code type tags to direct the disassembly to the proper ARM/THUMB output.
Post 08 Oct 2013, 05:49
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nop



Joined: 01 Sep 2008
Posts: 165
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nop
awsum work uart777 u shud be congratralated Cool and best wishes 4 ur happy bday Wink
Post 08 Oct 2013, 06:02
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HaHaAnonymous



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HaHaAnonymous
[ Post removed by author. ]


Last edited by HaHaAnonymous on 28 Feb 2015, 19:47; edited 1 time in total
Post 08 Oct 2013, 12:29
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MHajduk



Joined: 30 Mar 2006
Posts: 6038
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MHajduk
Happy Birthday uart777, you are the Libra like me and the Snake accordingly to the Chinese zodiac. Wink

Referring to the application itself, I think I got what you mean when you were grumbling about too much OS oriented programming. I'm going to separate input/output functions from the code and form there as macros analogically to what you have done.
Post 08 Oct 2013, 15:01
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uart777



Joined: 17 Jan 2012
Posts: 369
uart777
On Android phone. Netbook modem went out 3 weeks ago. No internet access in Ubuntu+Puppy, either.

nop and MHjaduk: Thanks. I appreciate it.

revolution: No thumb encodings yet. User could select CPU state: (*) ARM () Thumb1/2 () Mixed (Assume). Settings are easily customizable at end of DARM7.INC. Just add command to list then "if setting".

While I was learning ARM, I would've loved to have a disassembler that supports this much. ARMu disassembler (google) doesnt even recognize v5 and theres no way to copy/access ASM output whereas this can produce working FASMARM code from raw binary.


Last edited by uart777 on 08 Oct 2013, 17:46; edited 1 time in total
Post 08 Oct 2013, 17:39
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uart777



Joined: 17 Jan 2012
Posts: 369
uart777
Mistake: By default, DARM7.ASM reloads TEST.BIN. Forgot to remove "text.copy filename, default.file" before "disassemble filename".
Post 08 Oct 2013, 17:45
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uart777



Joined: 17 Jan 2012
Posts: 369
uart777
revolution: Now that I think about it, we could use an instruction that is "permanently undefined" in both ARM+Thumb to mark the beginning and end of such procedures (or breakpoint/bkpt with a certain #. example: OxAB/0xAE = ARM begin/end)
Post 08 Oct 2013, 18:11
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17641
Location: In your JS exploiting you and your system
revolution
uart777 wrote:
revolution: Now that I think about it, we could use an instruction that is "permanently undefined" in both ARM+Thumb to mark the beginning and end of such procedures (or breakpoint/bkpt with a certain #. example: OxAB/0xAE = ARM begin/end)
I did a similar thing also but that only works for one's own code. When I have the source I find that I usually don't need the disassembly, so a disassembler is often used for code that we don't have the source for.

The general problem to solve with detecting ARM/THUMB is extremely difficult to solve from what I have seen. There is no reliable way to detect either of them by only looking at the instructions. Many of the binaries I have had needed a human eye to spot things and then direct the disassembler in an interactive process. You might be able to use some basic heuristics but the number of failures can easily outnumber the number of successes and make the whole thing futile in some cases. If you know for certain that a particular compiler/linker combination was used to make the binary then it might be possible to create a special filter to detect all the the interworking links but these types of special filters tend to become very cumbersome and bloated when one tries to make a general tool to support the multitude of compiler/linker combinations used.

The general plan of doing a multi-pass disassembly and trying to tag sections based upon BX, MOV, LDM, LDR etc. instructions seems to fail mostly because it is common for registers to be used as the target address. Unless one uses a VM to trace the code paths and register contents then such transfers become impossible to predict without some very deep analysis.

I am looking for a better technique to do automatic detection and would welcome any possible ideas.
Post 08 Oct 2013, 18:41
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17641
Location: In your JS exploiting you and your system
revolution
Additional: For an automated ARM/THUMB detector to work I think a brute force approach would be most promising. Anything that relies upon analysis is probably going to be too prone to failures. Humans are good at analysis and poor at brute force. And our current intelligence level cannot seem to infuse computers with the same analytical prowess as the human brain. I don't care if it takes many tens-of-seconds to produce a good disassembly by using "wasteful" brute force methods as long as it gets it right.
Post 08 Oct 2013, 20:04
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uart777



Joined: 17 Jan 2012
Posts: 369
uart777
Solution: bkpt # before/after function/procedure (wont get executed): 00AB=ARM begin, 00AE=ARM end, 00BB=Thumb/B begin, 00BE=Thumb end, 00FB=VFP begin, 00FE=VFP end.

Standard breakpoint could work like this: 0000=Breakpoint, RRR1=with reason # (ie, "Divide by zero', 'Null pointer').

Sorry for multiple posts. On Android phone.
Post 08 Oct 2013, 20:07
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uart777



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Posts: 369
uart777
Oh and 00DB=Data begin. 00DE=Data end. So, it will never interpret data as code.
Post 08 Oct 2013, 20:11
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17641
Location: In your JS exploiting you and your system
revolution
uart777 wrote:
Solution: bkpt # before/after function/procedure (wont get executed): 00AB=ARM begin, 00AE=ARM end, 00BB=Thumb/B begin, 00BE=Thumb end, 00FB=VFP begin, 00FE=VFP end.
Sure, but this works only when you have the original source, and thus when disassembly is probably not even needed. What about a random binary file where such markers are not included?
Post 08 Oct 2013, 20:16
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sleepsleep



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sleepsleep
uart777 wrote:
D-ARM7 Disassembler

Today is my birthday Smile 3 consecutive 7s: 10-7


happy birthday to u uart777 Wink
take care there.
Post 08 Oct 2013, 23:55
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TmX



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Posts: 822
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TmX
uart777 wrote:

Today is my birthday Smile 3 consecutive 7s: 10-7-77. Promised myself I'd release it before this day. Time: 12-15 hours, average 1-3 hours a day for about a week.


And this assembler makes a nice milestone.
Congratulations. Smile
Post 09 Oct 2013, 03:54
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uart777



Joined: 17 Jan 2012
Posts: 369
uart777
Thanks everyone.

revolution: I know, you can't differentiate between ARM/Thumb just by looking at it. But is there a way to be right 90% of the time? You could do a statistical analysis on bigger ARM programs (ie, Linux) to determine the frequency of instructions then arrange them by priority. Most popular may be mov, ldr, push, cmp, bxx, add, etc. Then compare the list of the most common ARM encodings versus Thumb. If it matches more popular ARM encodings in the entire file, then in theory, it's more likely to be ARM.

A disassembler is useful for debugging my own source code/languages/libraries, as valuable as it is to C/C++ programmers. When an exception occurs, I want to know the exact address, which function it's in and see the pure ASM, not data. It also helps beginners to learn which are pseudo instructions and it can be used to generate code for books/tutorials.
Post 09 Oct 2013, 04:21
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uart777



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Posts: 369
uart777
UPDATE

* Minimal Thumb (T1) support (option: t1).
* HTML output (option: html)
* Bug fix: str[sp,-#]! was incorrectly indentified as msr
* Improved source clarity
* If a1-v8, ip (general) is now the default name for r12

See attachment.

Thumb Disassembly
Code:
00000000 0000 dh 0
00000002 BF00 nop
00000004 BECC bkpt 0CCh
00000006 DF77 svc 77h
00000008 1C37 mov r7, r6
0000000A 27AB mov r7, 0ABh
0000000C 43D1 mvn r1, r2
0000000E A704 adr r7, 20h
00000010 A705 adr r7, 28h
00000012 E003 b 1Ch
00000014 D003 beq 1Eh
00000016 DC03 bgt 20h
00000018 4708 bx r1
0000001A 4790 blx r2
0000001C B4FF push {r0-r7}
0000001E BCFF pop {r0-r7}
00000020 B49B push {r0-r1,r3-r4,r7}
00000022 BC9B pop {r0-r1,r3-r4,r7}
00000024 B187 cbz r7, 48h
00000026 B98F cbnz r7, 4Ch
00000028 6811 ldr r1, [r2]
0000002A 5CD1 ldrb r1, [r2, r3]
0000002C 8811 ldrh r1, [r2]
0000002E 56D1 ldrsb r1, [r2, r3]
00000030 5ED1 ldrsh r1, [r2, r3]
00000032 50D1 str r1, [r2, r3]
00000034 54D1 strb r1, [r2, r3]
00000036 52D1 strh r1, [r2, r3]
00000038 18D1 add r1, r2, r3
0000003A 1AD1 sub r1, r2, r3
0000003C 3103 add r1, 3
0000003E 3907 sub r1, 7
00000040 3180 add r1, 80h
00000042 39EE sub r1, 0EEh
00000044 4151 adc r1, r2
00000046 4191 sbc r1, r2
00000048 4351 mul r1, r2
0000004A 4011 and r1, r2
0000004C 4311 orr r1, r2
0000004E 4051 eor r1, r2
00000050 4391 bic r1, r2
00000052 4091 lsl r1, r2
00000054 40D1 lsr r1, r2
00000056 4111 asr r1, r2
00000058 41D1 ror r1, r2
0000005A 4211 tst r1, r2
0000005C 4291 cmp r1, r2
0000005E 42D1 cmn r1, r2
00000060 B211 sxth r1, r2
00000062 B251 sxtb r1, r2
00000064 B291 uxth r1, r2
00000066 B2D1 uxtb r1, r2
00000068 BA11 rev r1, r2
0000006A BA51 rev16 r1, r2
0000006C BAD1 revsh r1, r2
0000006E BF10 yield 
00000070 BF20 wfe 
00000072 BF30 wfi 
00000074 BF40 sev 
00000076 B650 setend le    
FASMARM's ARMPE4.EXE
Code:
00000000 E92D5FFF stmdb  sp!,{a1-ip,lr}
00000004 E24DDB01 sub    sp,sp,0x400
00000008 E28DA000 add    v7,sp,0
0000000C E3A04000 mov    v1,0
00000010 E3A00052 mov    a1,0x52
00000014 E0CA00B2 strh   a1,[v7],2
00000018 E1A01004 mov    a2,v1
0000001C E1A0000A mov    a1,v7
00000020 EB00003C bl     0x118
00000024 E240A002 sub    v7,a1,2
00000028 E28F10C8 add    a2,pc,0xC8
0000002C E1A0000A mov    a1,v7
00000030 EB000033 bl     0x104
00000034 E240A002 sub    v7,a1,2
00000038 E354000D cmp    v1,0xD
0000003C B28D5B01 addlt  v2,sp,0x400
00000040 B7956104 ldrlt  v3,[v2,v1,lsl 2]
00000044 059F607C ldreq  v3,[pc,0x7C]
00000048 008D6006 addeq  v3,sp,v3
0000004C E354000E cmp    v1,0xE
00000050 059D6434 ldreq  v3,[sp,0x434]
00000054 824F605C subhi  v3,pc,0x5C
00000058 E3A02008 mov    a3,8
0000005C E1A01006 mov    a2,v3
00000060 E1A0000A mov    a1,v7
00000064 EB00003D bl     0x160
00000068 E240A002 sub    v7,a1,2
0000006C E28F1088 add    a2,pc,0x88
00000070 E1A0000A mov    a1,v7
00000074 EB000022 bl     0x104
00000078 E240A002 sub    v7,a1,2
0000007C E1A01006 mov    a2,v3
00000080 E1A0000A mov    a1,v7
00000084 EB000023 bl     0x118
00000088 E240A002 sub    v7,a1,2
0000008C E28F106B add    a2,pc,0x6B
00000090 E1A0000A mov    a1,v7
00000094 EB00001A bl     0x104
00000098 E240A002 sub    v7,a1,2
0000009C E2844001 add    v1,v1,1
000000A0 E354000F cmp    v1,0xF
000000A4 9AFFFFD9 bls    0x10
000000A8 E3A03000 mov    a4,0
000000AC E28F2018 add    a3,pc,0x18
000000B0 E28D1000 add    a2,sp,0
000000B4 E3A00000 mov    a1,0
000000B8 E1A0E00F mov    lr,pc
000000BC E59FFF70 ldr    pc,[pc,0xF70]
000000C0 E28DDB01 add    sp,sp,0x400
000000C4 E8BD9FFF ldmia  sp!,{a1-ip,pc}

00000104 E4D12001 ldrb   a3,[a2],1
00000108 E0C020B2 strh   a3,[a1],2
0000010C E3520000 cmp    a3,0
00000110 1AFFFFFB bne    0x104
00000114 E12FFF1E bx     lr

00000118 E3E0C032 mvn    ip,0x32
0000011C E3CCCC33 bic    ip,ip,0x3300
00000120 E3A03000 mov    a4,0
00000124 E08CC80C add    ip,ip,ip,lsl 16
00000128 E56D3001 strb   a4,[sp,-1]!
0000012C E1A02001 mov    a3,a2
00000130 E081319C umull  a4,a2,ip,a2
00000134 E1B011A1 movs   a2,a2,lsr 3
00000138 E0423181 sub    a4,a3,a2,lsl 3
0000013C E0433081 sub    a4,a4,a2,lsl 1
00000140 E2833030 add    a4,a4,0x30
00000144 1AFFFFF7 bne    0x128
00000148 E0C030B2 strh   a4,[a1],2
0000014C E4DD3001 ldrb   a4,[sp],1
00000150 E3530000 cmp    a4,0
00000154 1AFFFFFB bne    0x148
00000158 E0C030B2 strh   a4,[a1],2
0000015C E12FFF1E bx     lr

00000160 E16F3F11 clz    a4,a2
00000164 E2633023 rsb    a4,a4,0x23
00000168 E3520008 cmp    a3,8
0000016C 83A02008 movhi  a3,8
00000170 E3520000 cmp    a3,0
00000174 03C32003 biceq  a3,a4,3
00000178 11A02102 movne  a3,a3,lsl 2
0000017C E2422004 sub    a3,a3,4
00000180 E1A03271 mov    a4,a2,ror a3
00000184 E203300F and    a4,a4,0xF
00000188 E2833030 add    a4,a4,0x30
0000018C E3530039 cmp    a4,0x39
00000190 82833007 addhi  a4,a4,7
00000194 E0C030B2 strh   a4,[a1],2
00000198 E3520000 cmp    a3,0
0000019C CAFFFFF6 bgt    0x17C
000001A0 E3A03000 mov    a4,0
000001A4 E0C030B2 strh   a4,[a1],2
000001A8 E12FFF1E bx     lr    


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darm7.jpg


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Filename: d-arm7.zip
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Last edited by uart777 on 12 Oct 2013, 08:58; edited 1 time in total
Post 12 Oct 2013, 07:28
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uart777



Joined: 17 Jan 2012
Posts: 369
uart777
DARM7.ASM:
Code:
; D-ARM7 Lite Disassembler

include 'z.inc'
include 'darm7.inc'

text filename(256),\
 test.bin='TEST.BIN',\
 thumb.bin='THUMB.BIN',\
 destiny.file='DASM.TXT'

filter: db \
 'Binary (*.BIN)', 0, '*.BIN', 0,\
 'Image (*.IMG)', 0, '*.IMG', 0,\
 'ARM (*.AIF)', 0, '*.AIF', 0,\
 'Mobile (*.EXE)', 0, '*.EXE', 0,\
 'All (*.*)', 0, '*.*', 0, 0

;;;;;;;;;;;;;;;;;; DISASSEMBLE ;;;;;;;;;;;;;;;;;;;

function disassemble, name
 locals p, i, n, x, size

 try [source]=load.file [name]

 let eax=[file.n]
 .if [@state]='t'
   let eax>>>1
 .else
   let eax>>>2
 .end
 let [n]=eax, eax*256, [size]=eax,\
  eax=[@base], [@ip]=eax

 try [destiny]=allocate [size] ; allocate

 let [p]=eax, byte [eax]=0

 .loop [i]=0 to [n]            ; # instructions
   let eax=[source],\
    ecx=[i]
   .if [@state]='a'            ; ARM
     let ecx*4,\
      ecx+[@start]
     dasm [eax+ecx]
   .else.if [@state]='t'       ; Thumb T1
     let ecx*2,\
      ecx+[@start],\
      edx=0, dx=[eax+ecx]
     dasm.t1 edx
   .end
   text.attach [p], dasm.t     ; line
   .if [case?]                 ; uppercase?
     text.upper [p]            ; convert
     @@:
     .if.text.search \         ; 0X?
       [p], bad.hex.t          ; replace
       let byte [eax+1]='x'    ; with 0x
       jmp @b
     .end
   .end
   text.attach.nl [p]          ; new line
   .if [@state]='a'            ; advance
     let [@ip]+4
   .else.if [@state]='t'
     let [@ip]+2
   .end
   let eax=[@end]              ; end point?
   .if true
     .if [@ip]>eax
       jmp .out
     .end
   .end
   .el:
 .endl
 .out:
 save.text destiny.file, [destiny]
 destroy [source], [destiny]
endf [n]

;;;;;;;;;;;;;;;;;;;;;; HTML ;;;;;;;;;;;;;;;;;;;;;;

html.ext db '.HTML', 0

html.begin db \
 '<html><head></head><body>',\
 '<b><font face="Courier New"',\
 'size=5 color="#000000"><pre>', 0

html.end db \
 '</pre></b></body></html>', 0

font.color.t db '<font color="#%t">', 0
font.end.t db '</font>', 0

macro html.set.color c {
 convert.n2t.a c, t2, 'h', 6
 print t, font.color.t, t2
 write.texts t
}

macro html.end.color
 { write.text font.end.t }

; write .HTML file. # instructions

function create.html, file, n
 locals p
 text.copy t, [file]
 try [p]=load.text t
 remove.ext t
 text.attach t, html.ext
 text.copy destiny.file, t
 create t
 write.texts html.begin, NL
 html.set.color 7F0417h
 write.text [p]
 html.end.color
 write.text html.end
 destroy [p]
 close
endf 1

; get filename from command line...

function get.filename
 set.source [command.line]
 let [source]++               ; skip first "
 copy.until.c '"'             ; module name
 let [source]+2, eax=[source] ; skip '" ' after
 .if byte [eax]=0             ; no parameters?
   set.file.filter filter
   choose.file filename, 'o'
   .if false
     exit
   .end
   return
 .end
 let [source]+2               ; skip first "
 copy.until.c ' '             ; get parameter
 text.copy filename, [token]
 settings [source]            ; settings
endf

; main...

function main
 locals n
 get.filename
 text.ends filename, thumb.bin
 .if true
   let [@state]='t'
 .end
 try [n]=disassemble filename
 .if [html?]
   create.html destiny.file, [n]
 .end
 .if not [silent?]
   execute destiny.file
 .end
endf    
Post 12 Oct 2013, 07:42
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uart777



Joined: 17 Jan 2012
Posts: 369
uart777
UPDATE

* Bug fix: Load/store multiple with one register ({r0}), push/pop A2
* View pure binary code in ARM+Thumb (option: binary)

Binary:
Code:
0010011110101011 mov r7, 0ABh
0001100011010001 add r1, r2, r3
0110100000010001 ldr r1, [r2]
0101110011010001 ldrb r1, [r2, r3]
1011010010011011 push {r0-r1,r3-r4,r7}
1011110010011011 pop {r0-r1,r3-r4,r7}

11100011001000001111000000000000 nop
11100001001000010010001101110100 bkpt 1234h
11100001101000000001000000000010 mov r1, r2
11100011000000010111001000110100 movw r7, 1234h
11100011100000100001000100000010 orr r1, r2, 80000000h
11000000100000100001010000010011 addgt r1, r2, r3, lsl r4
11100011010100010000100001111111 cmp r1, 0x7F0000    


Description:
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Filename: d-arm7.zip
Filesize: 97.56 KB
Downloaded: 1093 Time(s)

Post 13 Oct 2013, 06:54
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