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Index > Non-x86 architectures > Any comment on Arm Core initialization?

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cwpjr



Joined: 03 Jul 2012
Posts: 45
cwpjr
This may be hay but I hope to ask about setting up bare metal scaffolding for running asm, more specifically setting BB init evironments for NXP1114 thru say STMF4 level cores (M0-M4).

My inclinations is to wish for the same intvecs. hahaha.

So my question is about the commonality of the INT Vectors.

Do the ARM cores in the M0-M4 range share 'core' (COLD at zero, thru some standard subset) int vec, ordered such that varaiant functions are tagged on to the end of the intvec's?

Or does each variant have it's own to cope with?

TIA, (Thanks In Advance), Clyde

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Post 07 Dec 2012, 03:52
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 16931
Location: In your JS exploiting you and your system
revolution
cwpjr wrote:
Do the ARM cores in the M0-M4 range share 'core' (COLD at zero, thru some standard subset) int vec, ordered such that varaiant functions are tagged on to the end of the intvec's?
All ARM cores have the standard set of interrupt vectors.
Code:
vectors:
   b       power_up_reset
      b       undefined_instruction
       b       SWI_or_SVC
  b       prefetch_abort
      b       data_abort
  nop
 b       irq
 b       fiq    
Post 08 Dec 2012, 05:14
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cwpjr



Joined: 03 Jul 2012
Posts: 45
cwpjr
As it should be. Tx. Documentation from ARM does not address commonalities very well I think.
In trying to do simple LED tests on eval kit boards in ASM I reviled the cut and paste documentation on the Control Registers for the GPIO where for each bit the doc simply states 'set this bit for this functionality', all the while my knowledge tells me many will do just that and brick their devices, because the other bits matter in every update/usage!
Post 20 Feb 2013, 01:48
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