flat assembler
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      > OS Construction > IRQs in Pmode | 
  
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                   revolution 13 Jun 2011, 11:37 
                  BOTOKILLER wrote: ... I will have to map them somehow, how??? Intel Manual 3A, Chapter 6, Section 10 "INTERRUPT DESCRIPTOR TABLE (IDT)"  | 
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                   BOTOKILLER 13 Jun 2011, 14:55 
                  I know that I have to use IDT, but what interrupt numbers IRQs occupy??? 
                  
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                   revolution 13 Jun 2011, 15:11 
                  I assume then that you are asking about the hardware interrupt numbers? If so then you need to program the PIC chips to set the base value. 
                  
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                   Dex4u 13 Jun 2011, 15:17 
                  Yes you need to remap them, something like this:
 
                  
                Code: remap_pic: cli mov al,0x11 ; put both 8259s in init mode out 0x20,al out 0xA0,al mov al,0x20 ; remap pic irq0-irq7 -> int 0x20-27 out 0x21,al mov al,0x28 out 0xA1,al ; remap pic irq8-irq15 -> int 0x28-30 mov al,4 ; icw3 pic1(master) out 0x21,al ; bit 2=1: irq2 is the slave mov al,2 ; icw3 pic2 out 0xA1,al ; bit 1=1: slave id is 2 mov al,1 ; icw4 to both controllers out 0x21,al ; bit 0=1: 8086 mode out 0xA1,al mask_irqs: cli mov al,255 ; mask all irqs out 0xa1,al out 0x21,al ret  | 
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                   BOTOKILLER 15 Jun 2011, 12:08 
                  Dex4u wrote: Yes you need to remap them, something like this: thanks works fine, but mask must be 0, so that interrupts work  | 
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                   Dex4u 15 Jun 2011, 15:40 
                  BOTOKILLER wrote: 
 Which in most cases it all of them. Code: unmask_irqs: mov al,0 ; unmask irq's out 0xA1,al out 0x21,al sti ret But not always  | 
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                   christiandy 14 Jul 2011, 18:08 
                  My IRQs can call in software interrupt but not working in hardware interrupt I used exactly same with this code. do you know why? 
                  
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                   cod3b453 22 Jul 2011, 19:15 
                  ISRs require a valid GDT and IDT as well as interrupts being enabled. IRQs have an additional enable by writing 0 to their mask bit in their respective  registers (Intel 8259 ports 0x20,0xA0) [writing 1 disables them]. 
 
                  
                Note the above code simply remaps the IRQs and disables (masks) them.  | 
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                   Dex4u 22 Jul 2011, 19:50 
                  You also need to send a end of IRQ 
 
                  
                Eg: Code: mov al,0x20 out 0xa0,al out 0x20,al At the end of every IRQ handler, or you will only get one firing, once.  | 
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