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Azu



Joined: 16 Dec 2008
Posts: 1160
Azu
mattst88 wrote:
Dude, really?
"Yes, typos are bad and all, but teh important thing is that you understand others, and others understand you."

The above response is better than;

"What are you talking about? I don't get it.."


No?
Post 05 Apr 2009, 23:37
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Borsuc



Joined: 29 Dec 2005
Posts: 2466
Location: Bucharest, Romania
Borsuc
I don't make the error and am not even native english speaker Razz
Post 06 Apr 2009, 16:42
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Azu



Joined: 16 Dec 2008
Posts: 1160
Azu
Okay..? Anyways, I wasn't talking to either of you guys, so back off already.
Was talking to that guy |
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tom tobias wrote:
revolution wrote:
L1 access time ~ 3 clock cycles, L2 ~ 9, SDRAM ~ 40-50, HDD >100000. SDRAM is slow

"slow" ???
slower than what?



Hench why I clearly quoted his post in my reply.. not sure how you missed it..
Post 06 Apr 2009, 16:59
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Borsuc



Joined: 29 Dec 2005
Posts: 2466
Location: Bucharest, Romania
Borsuc
Why so serious? Wink

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Previously known as The_Grey_Beast
Post 07 Apr 2009, 23:15
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Azu



Joined: 16 Dec 2008
Posts: 1160
Azu
Why so trollish?
Post 07 Apr 2009, 23:17
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bitRAKE



Joined: 21 Jul 2003
Posts: 2914
Location: [RSP+8*5]
bitRAKE
tom tobias wrote:
allow me to speculate for the future:
a. newly designed "cpu" integrated into the memory controller itself, will change that relationship, ultimately the entire memory will be cache.
b. in the intermediate future, cpu architecture dictates the relationship between motherboard components, including sdram, hence, newer cpu designs will reduce the existing bottleneck, and sdram access times will decrease in newer cpus in the future.
The reality is quite different: Intel/AMD are using deeper cache topologies to improve communication between cores while (only) maintaining existing (per core) cache latencies. Memory controller integration helps counter the memory bus being further away. Reducing latencies in a shared core environment will be much more difficult - hence the need to utilize NUMA. Anyone can buy as much throughput as they want, but latency is a caching game - always will be.
Post 08 Apr 2009, 03:37
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