flat assembler
Message board for the users of flat assembler.
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revolution
IIRC EOI releases the INTR request at the hardware level and allows for the detection of the next lower priority request. If you don't release the INTR with EOI then you get stuck in a loop of servicing interrupt requests because the CPU thinks the interrupt is still active.
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Japheth
revolution wrote: If you don't release the INTR with EOI then you get stuck in a loop of servicing interrupt requests because the CPU thinks the interrupt is still active. That's not quite correct. The EOI is intended for the PIC only. If no EOI is sent to the PIC then the PIC thinks the interrupt is still pending and the CPU will receive no further IRQs. You can easily test what's going on in the PIC by reading its IRR (interrupt request register) and ISR (interrupt service register). After EOI is sent to the PIC, the bit in the ISR of the currently handled IRQ will change. |
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bitRAKE
It has been a long time since I read the docs, but isn't there some way to set the triggering to where the PIC assumes the IRQ will be handled? I thought there was four triggering modes, but one that is used by most everyone.
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DOS386
Japheth wrote: That's not quite correct. The EOI is intended for the PIC only. If no EOI is sent to the PIC then the PIC thinks the interrupt is still pending and the CPU will receive no further IRQs. Thanks. CPU will receive no further what exactly ? IRQ's of same type ? Of lower priority ? Any IRQ at all ? |
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bitRAKE
It would be same type or higher priority, iirc.
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revolution
DOS386 wrote:
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bitRAKE
I miss read Japheth's reply:
If no EOI is sent then only higher priority IRQ's can be sent by the PIC - same and lower priority IRQ's will be blocked. |
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