flat assembler
Message board for the users of flat assembler.
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revolution 22 Dec 2008, 01:51
You can also use FCMOVcc. Since you are using 64bit code then FCMOV will be available.
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bitRAKE 22 Dec 2008, 01:54
How does it look penalty-wise though?
Almost as bad as a branch, iirc. (Off through the Fog I go...) Edit: doc says 2 cycles! There is a winner. |
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revolution 22 Dec 2008, 01:59
Penalties would depend upon the CPU being used. You need to define more the parameters of the test.
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LocoDelAssembly 22 Dec 2008, 02:15
Quote:
This assumption should be normally safe, but the documentation says: AMD wrote: Use the CPUID instruction to determine if this instruction is supported on a |
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revolution 22 Dec 2008, 02:21
Hehe, okay:
You can also use FCMOVcc. Since you are using 64bit code then FCMOV will most likely be available. |
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mattst88 23 Dec 2008, 02:05
I don't believe any 64-bit x86 CPUs exist without a floating-point unit, much less FCMOVcc instuctions.
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revolution 23 Dec 2008, 02:38
mattst88 wrote: I don't believe any 64-bit x86 CPUs exist without a floating-point unit, much less FCMOVcc instuctions. ![]() |
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bitRAKE 02 Feb 2009, 07:10
Windows defaults to 53-bit mode, so if anyone (myself, for example) attempts to use any of this code be sure to change to extended precision.
Code: push 0 fnstcw [rsp] and word [rsp],-1 - 1100000000b or word [rsp], 1100000000b ; double extended precision fldcw [rsp] pop rax |
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LocoDelAssembly 02 Feb 2009, 18:22
bitRAKE, is the AND instruction really necessary for something?
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bitRAKE 02 Feb 2009, 20:10
No, just the crust from some cut-n-paste. As you noticed, it doesn't do anything since all the bits effected are just being set - OR is sufficient. Could use PUSH R?? as well to reduce the size. Or maybe gamble with (or a 00 03 somewhere in the code):
Code: push 11b fldcw [rsp-1] pop rax |
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revolution 02 Feb 2009, 20:40
Changing the precision may bit be needed. It only seems to affect the div & sqrt that I can tell. Perhaps also the transcendental functions?
FADDs, FSUBs, FMULs and most others won't be affected. |
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bitRAKE 02 Feb 2009, 21:52
Intel 8.1.5.2 wrote: The precision-control bits only affect the results of the following floating-point instructions: FADD, FADDP, FIADD, FSUB, FSUBP, FISUB, FSUBR, FSUBRP, FISUBR, FMUL, FMULP, FIMUL, FDIV, FDIVP, FIDIV, FDIVR, FDIVRP, FIDIVR, and FSQRT. |
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revolution 03 Feb 2009, 00:00
bitRAKE wrote:
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