Hello. Can somebody tell me what the differences between PL1, PL2, and PL3 (x86 Coders: ring 1, ring 2, ring 3)? Normally, I see in both the Intel 64 (Xeon-ish) architecture manuals and IA-64 architecture manuals that there are a lot of "system instructions" that can only be accessed "at the lowest privelege level"

I was wondering if there is any hardware-style differences between PL1, PL2, and PL3 (x86 Coders: ring 1, ring 2, ring 3) or can any of them be used for user applications.

Basically, I'm developing a microkernel where I want all the important kernel services (scheduling, basic IPC, basic memory management, SMP support) to run in PL0, and all the device drivers, applications, server processes, etc to run in user mode.

When I say user mode, I mean well protected from the kernel (PL3/ring 3 level protection)

I was wondering if PL1, PL2, and PL3 (x86 Coders: ring 1, ring 2, ring 3) are the same. I am assuming they PL# (Itanium) is the same as ring # (x86)

Or does PL1/ring 1 have more access to instructions than PL2/ring 2, which has more access than PL3/ring 3?

I want to assign the privelege levels to the following classes of processes.

If PL1/PL2/PL3 are the same:

PL0 = Kernel
PL1 = Core and Driver Processes
PL2 = System Services
PL3 = User Applications and Services

If PL1/PL2/PL3 are different as far as instruction and low level register/hard ware access is concerned:

PL0 = Kernel
PL1 = Core, Driver Processes, System Services, User Applications and Services

I would appreciate your help!

Ring0 is the only hardware-based privileged level. The other rings are purely software managed access levels. The most obvious advantage is the setting IOPL for something like a driver running in ring1. This could allow a driver to access I/O ports but not be able to change CRx.