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madmatt



Joined: 07 Oct 2003
Posts: 1045
Location: Michigan, USA
madmatt
I'm beginning to use the sse instructions on my AMD and tried to use the instruction 'movups', which gave me an invalid opcode esception. Has anyone else tested this instruction?
Post 26 Jan 2004, 19:12
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comrade



Joined: 16 Jun 2003
Posts: 1137
Location: Russian Federation
comrade
Compiled fine like so:
Code:
movups  xmm1,xmm2    

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comrade (comrade64@live.com; http://comrade.ownz.com/)
Post 26 Jan 2004, 21:17
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madmatt



Joined: 07 Oct 2003
Posts: 1045
Location: Michigan, USA
madmatt
I'm using it this way:
Code:
movups [es:esi],xmm0    

It should take a memory operand (and selector) as well
My program would compile fine too, but when executed, would generate an invalid opcode exception. By the way the selector is valid or it would generate another type of exception.
Post 26 Jan 2004, 22:47
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Tomasz Grysztar



Joined: 16 Jun 2003
Posts: 7725
Location: Kraków, Poland
Tomasz Grysztar
Are you sure your processor has the SSE extension? The most of the AMD processors (except for the recent ones) have only 3DNow! in addition to elementary MMX.
Post 26 Jan 2004, 22:49
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madmatt



Joined: 07 Oct 2003
Posts: 1045
Location: Michigan, USA
madmatt
It should, It is an AMD AthlonXP 2300+ Model 8, which has the sse instruction set, I set variables using the cpuid instruction, and printing out the variables shows that I have the sse instruction set.
Just looked at the PIV Instruction set manual:

0F 10 /r MOVUPS xmm1, xmm2/m128 Move packed single-precision floating-point values
from xmm2/m128 to xmm1.
0F 11 /r MOVUPS xmm2/m128, xmm1 Move packed single-precision floating-point values
from xmm1 to xmm2/m128.

I think I found what I am doing wrong. I should be using the xmm1 register instead of xmm0. hmm, I'll try and see.
Post 27 Jan 2004, 06:24
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Tomasz Grysztar



Joined: 16 Jun 2003
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Location: Kraków, Poland
Tomasz Grysztar
No, xmm1 and xmm2 there just mean that you can use any xmm register as destination and any other as source.
I have checked the encodings and everything seems to OK, so perhaps your processor really doesn't support this instruction.
Post 27 Jan 2004, 10:03
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madmatt



Joined: 07 Oct 2003
Posts: 1045
Location: Michigan, USA
madmatt
Privalov wrote:
No, xmm1 and xmm2 there just mean that you can use any xmm register as destination and any other as source.
I have checked the encodings and everything seems to OK, so perhaps your processor really doesn't support this instruction.


I checked the system info and this is what I have:
Processor x86 Family 6 Model 8 Stepping 1 AuthenticAMD ~1995 Mhz
I checked the amd cpuid reference which says Model 6,8,10 should have the sse instruction set
There IS a side note though that says: sse instruction support is only present when the processor is set up to support it. <- What would this mean?
Post 27 Jan 2004, 12:02
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madmatt



Joined: 07 Oct 2003
Posts: 1045
Location: Michigan, USA
madmatt
Hello,
I figured out whats is going on, and everything works OK now. WHEW!
Privalov, you may want to include the following text in your fasm manual about using the AMD sse instruction set in dos mode:

Quote:
Use of the 128-bit media instructions requires system software
to support SSE and/or SSE2 features, but also the FXSAVE and
FXRSTOR instructions, which are used to save and restore the
128-bit media state (see “FXSAVE and FXRSTOR Instructions
on page 351). When these instructions are supported, system
software must set CR4.OSFXSR=1 to let the processor know
that the software uses these instructions. When the processor
detects CR4.OSFXSR=1, it allows execution of the 128-bit
media instructions. If system software does not set
CR4.OSFXSR to 1, attempts to execute 128-bit media
instructions cause an invalid-opcode exception (#UD).

-----------
Quote:
The CR4 bit you need to set to enable the AMD sse instruction set in dos mode:
set bit 9 [mov eax,cr4 : or eax,$200 : mov cr4,eax]


Thanks to everyone for there help!
Post 27 Jan 2004, 14:57
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chaoscode



Joined: 21 Nov 2006
Posts: 64
chaoscode
How can I say M$ Windows (xp sp2) that i want to use SSE?
Post 15 Jul 2007, 16:52
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LocoDelAssembly
Your code has a bug


Joined: 06 May 2005
Posts: 4633
Location: Argentina
LocoDelAssembly
If your processor supports it just use it. WinXP is aware of SSE.
Post 15 Jul 2007, 18:10
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chaoscode



Joined: 21 Nov 2006
Posts: 64
chaoscode
My Processor supports SSE, but every time i want to use
Code:
movaps xmm0,[eax]    
i get a illegal Instruction Exception. (ollydbg)
My app reads CPUID and test it, WCPUID and other Apps say, my CPU (AMD Duron 1,8 GHZ) suport SSE
Post 15 Jul 2007, 18:40
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LocoDelAssembly
Your code has a bug


Joined: 06 May 2005
Posts: 4633
Location: Argentina
LocoDelAssembly
I just tried disabling SSE/SSE2 on BIOS and used this code:
Code:
include 'win32ax.inc'

start:
  mov     eax, 1
  cpuid
  test    edx, 1 shl 24
  jz      .notSupported

  ; To check if OS also supports we use a SSE instruction
  movaps  xmm0, xmm0

  invoke  MessageBox, 0, "SSE Supported", "SSE Detection", 0

  ret

.notSupported:
  invoke  MessageBox, 0, "SSE not supported", "SSE Detection", 0

  ret
.end start    


MessageBox reported: "SSE not supported". So check your BIOS settings because is very likely that it is your BIOS configuration the problem or the BIOS is buggy or old and does not perform the proper CPU initialization. Perhaps you will need to flash a new BIOS if you don't find any configuration related to SSE (or add some master boot code that enables SSE before Windows starts).

[edit]Well the code is wrong :$ Anyway when I tried using movaps with SSE/SSE2 disabled on BIOS the program crashed.[/edit]

[edit2]Changed code. After disabling SSE on BIOS the program crashes :S Apparently CPUID always will report that SSE is available while Windows respect BIOS's desition of not allow its use. I'm a little surprised because I was specting that CPUID will not inform support anymore but certainly not. Note however that SSE2 and SSE3 are reported as not supported but by some reason SSE is still reported as supported :S :S[/edit2]
Post 15 Jul 2007, 20:29
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LocoDelAssembly
Your code has a bug


Joined: 06 May 2005
Posts: 4633
Location: Argentina
LocoDelAssembly
Ah, this might be the problem of detecting SSE when actually it is disabled:
BIOS and Kernel Developer's Guide for AMD Athlon™ 64 and AMD Opteron™ Processors wrote:
Fast FXSAVE/FRSTOR Enable (FFXSE)—Bit 14. Enables the fast FXSAVE/FRSTOR
mechanism. A 64-bit operating system uses EDX bit 24 as returned by CPUID instruction
standard function 1
to determine the presence of this feature before enabling it. This bit is set
once by the operating system and its value is not changed afterwards. See “Register
Differences in Revisions of the AMD Athlon™ 64 and AMD Opteron™ Processors” on
page 29 for revision information about this field.


So enabling the SSEDIS bit in HWCR Register (MSR C001_0015h) does not disable the Fast FXSAVE/FRSTOR which is detected in the same way as SSE.

Still, I don't know why bit 25 in EDX is set...
[edit] I know now, it is because FXSAVE/FXRSTR is available and since them are SSE instructions then SSE is marked as available (which doesn't mean the full set). I also tried running some boot codes and even with proper BIOS settings bit 25 in EDX was cleared possibly meaning that this bit is activated once the bit in CR4 is enabled. I have to do more test to see at exactly which sitiations SSE is marked as available but I have no more time now Sad[/edit]
Post 15 Jul 2007, 21:06
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chaoscode



Joined: 21 Nov 2006
Posts: 64
chaoscode
i contacted amd, and they say, that my CPU supports SSE (1).
but whats wrong?
I use XP, and it should support SSE (you said).
but it doesent work.
is there an special thing, that i have no use?
a calll to windows for enabeling SSE?
or have i to use a CPU Driver from amd or whats wrong?

I have no option in my bios to disable SSE.
Post 17 Jul 2007, 13:57
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LocoDelAssembly
Your code has a bug


Joined: 06 May 2005
Posts: 4633
Location: Argentina
LocoDelAssembly
If you have bit 25 on EDX set on CPUID standard function 1 then it must be a BIOS problem IMHO (even if you don't have an option to disable SSE).

My CPU has SSEDIS bit but yours maybe has a bit to enable rather than disable. I can't found a BIOS and Kernel Developer's Guide for your CPU, only for Athlon64 Sad

If I found something I'll try to provide you a boot code that enables it so you boot from floppy, remove it and then you allow Windows to boot to see if this time SSE is reachable.
Post 17 Jul 2007, 14:30
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LocoDelAssembly
Your code has a bug


Joined: 06 May 2005
Posts: 4633
Location: Argentina
LocoDelAssembly
I found this at AMD Duron™ Processor Tech Docs
AMD Processor Recognition Application Note - For Processors Prior to AMD Family 0Fh Processors wrote:
Enabling SSE Support
All AMD Athlon™ XP and AMD Sempron™ processors fully support the SSE instruction set
extensions. This support is disabled by default; so, the BIOS must enable the feature. See the
AMD Athlon™ and AMD Duron™ Processor BIOS, Software, and Debug Developers Guide, order#
21656
. Motherboards will not pass AMD validation or be posted on the AMD recommended
motherboard Web site, if SSE is not enabled by the BIOS for model 6 and above processors.


If you found that manual then we can start to do something but I'm still not able to find it Sad
Post 17 Jul 2007, 15:18
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17287
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revolution
Don't forget that the memory address MUST be 16 byte aligned!
Post 19 Jul 2007, 10:30
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LocoDelAssembly
Your code has a bug


Joined: 06 May 2005
Posts: 4633
Location: Argentina
LocoDelAssembly
Quote:

Don't forget that the memory address MUST be 16 byte aligned!

Something that I should asked first...:$

chaoscode, "movaps xmm0, xmm0" also fails for you?
Post 19 Jul 2007, 15:53
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chaoscode



Joined: 21 Nov 2006
Posts: 64
chaoscode
I know the bug now.
i was a mistake by me *sorry*
i did a movupd instruction, which was dissassembled by ollydbg to a movups with a 0x66 prefix (or postfix? i don't now, what is what)
after i noticed this failure, i tryed a movups, and it works^^
Post 15 Apr 2008, 15:54
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