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DustWolf



Joined: 26 Jan 2006
Posts: 373
Location: Ljubljana, Slovenia
DustWolf
Hello,

I've been working on some hardware manipulation (working on a kernel) and have come to an interesting question:

When a CPU executes an IN or OUT instruction, what really happens?

The part that troubles me is the mechanism by which the CPU catches timing with peripherial devices siting on those input or output ports, which are slower than the CPU. They may even be slower than the bus they are on.

I was told each of these instructions only needs to be executed once, regardless of circumstances, even for devices that I know may reside on very slow buses. How does that work out? How does the device get two register flips controlled by OUT s to their ports, if the CPU sends two within one the device's clocks. Is the CPU waiting for the peripheral device to respond somehow before executing the next instruction?

Regardless, I would still like to know the complete process. No doubt there are some hardware gurus around here who know the whole thing precisely.

For example:
* AMD K8 on HyperTransport in nForce using HyperTransport: Does an OUT command to a port used by a graphics card on PCI-E bus running in full speed.
* Pentium 4 on an Intel chipset, Does an OUT command to a port used by an IDE controller sitting in an old PCI slot.
* Anything else: Does an IN instruction.

...what would be hardware the signaling involved?
Post 18 Jul 2008, 09:51
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17287
Location: In your JS exploiting you and your system
revolution
I suggest you download the spec manuals from Intel/AMD they describe the interface details including the bus timing. However, for the executive summary ...

Basically, it is all synchronised by the CPU in cooperation with the interface chipset.. When you try to execute multiple INs/OUTs in a sequence the CPU simply runs idle cycles until the next instruction can be put onto the bus. The chipset tells the CPU when the I/O cycle is finished thus allowing the CPU to move to the next bus cycle. It is the chipset that controls all the timing for each of the bus interfaces.
Post 18 Jul 2008, 10:46
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edfed



Joined: 20 Feb 2006
Posts: 4238
Location: 2018
edfed
CPU I/O share the same bus as memory addresses.

just, the difference is a I/O pin that indicate to hardware ( chipset ) that it is not a memory R/W but a port I/O.
Post 18 Jul 2008, 16:01
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DustWolf



Joined: 26 Jan 2006
Posts: 373
Location: Ljubljana, Slovenia
DustWolf
Need I point out your two answers are not particularly rich in details and apparently contradict eachother?
Post 19 Jul 2008, 02:29
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17287
Location: In your JS exploiting you and your system
revolution
DustWolf wrote:
Need I point out your two answers are not particularly rich in details and apparently contradict eachother?
For answers rich in details I think it more appropriate to refer to the source manuals.

As for contradictions, how do edfed's and my answers contradict each other? edfed points out the electrical connection of the signals. I point out the logical timing of the signals.
Post 19 Jul 2008, 06:47
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sinsi



Joined: 10 Aug 2007
Posts: 693
Location: Adelaide
sinsi
Think of memory-mapped I/O - writing to a linear address to access a port. The difference is, with I/O through ports on the bus, the I/O pin is active (as edfed pointed out) so it's not a memory read/write but a bus R/W.
Post 19 Jul 2008, 07:16
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DustWolf



Joined: 26 Jan 2006
Posts: 373
Location: Ljubljana, Slovenia
DustWolf
Nevermind the last post.. it was made at 5 am.

I understand. Basically, the CPU does wait, for the device at the other end, which is a chipset, which in turn may be waiting for something else. In other words, using I/O is reliable but it may be a weapon of mass cycle destruction if used "wrong".
Post 20 Jul 2008, 01:35
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17287
Location: In your JS exploiting you and your system
revolution
DustWolf wrote:
... using I/O is reliable but it may be a weapon of mass cycle destruction if used "wrong".
Oh yes, using I/O is a very reliable way to ensure that your code runs as fast as a lazy lethargic injured snail dragging a 1kg weight up a slippery hill against a gale-force headwind.
Post 20 Jul 2008, 03:22
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Azu



Joined: 16 Dec 2008
Posts: 1160
Azu
revolution wrote:
DustWolf wrote:
... using I/O is reliable but it may be a weapon of mass cycle destruction if used "wrong".
Oh yes, using I/O is a very reliable way to ensure that your code runs as fast as a lazy lethargic injured snail dragging a 1kg weight up a slippery hill against a gale-force headwind.
There must be an async way to do it though or operating systems would completely freeze whenever you copy a file or whatever.. right?
Post 07 Jun 2009, 09:14
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revolution
When all else fails, read the source


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Posts: 17287
Location: In your JS exploiting you and your system
revolution
DMA
Post 07 Jun 2009, 09:40
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