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matefkr



Joined: 02 Sep 2007
Posts: 1291
Location: Ukraine, Beregovo
matefkr
is there any cache for IDT in newer processors? (so that could fasten interrupts)
Post 18 Apr 2008, 08:52
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chaoscode



Joined: 21 Nov 2006
Posts: 64
chaoscode
i never heard about that,
but i think, that interrupts are usually not so often taken, so that a cache wouldn't imprvoe performance.(well, a amount off 200 Int's a second isn't very much for a today CPU)
Post 23 Apr 2008, 16:15
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daniel.lewis



Joined: 28 Jan 2008
Posts: 92
daniel.lewis
Well, I'm not an AMD chip architect, and I don't know the answer to your question.

I do know that the "int" instruction causes a jump into ring 0, which causes a rather large performance penalty, on the order of 100-900 cycles.

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Post 24 Apr 2008, 06:28
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f0dder



Joined: 19 Feb 2004
Posts: 3170
Location: Denmark
f0dder
I thought PL3 as well as conforming-code interrupts were possible, depending on how the IDT slots were set up? Smile
Post 24 Apr 2008, 08:35
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matefkr



Joined: 02 Sep 2007
Posts: 1291
Location: Ukraine, Beregovo
matefkr
And depending on the IOPL field as well right?
Post 25 Apr 2008, 09:09
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vid
Verbosity in development


Joined: 05 Sep 2003
Posts: 7105
Location: Slovakia
vid
If there was cache, i think there would also be need for syncing the cache after modifying IDT in memory - and I have never heard about that.
Post 25 Apr 2008, 09:30
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