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Madis731



Joined: 25 Sep 2003
Posts: 2140
Location: Estonia
Madis731
Okay - the VOL1 is a good read and a great introduction. VOL2 speaks about the pipelines very interestingly. VOL3 goes into detail to many registers and their usage, but most people get enough from VOL1 already. VOL4 is interesting because it has all the tables, images, lists about the instruction-set and its usage and maybe the most detailed one.

What I didn't find is how do I code a very primitive example. What are the steps, what is the process...say in 1024x768x32b@60Hz mode put a gray (808080h) pixel at position (3,2)?

Although I found that I can change LCD brightness and there's a reset 'button' (actually register).

EDIT:
Maybe its 31760701.pdf (Intel G35 Express Chipset) that I need to read or 31305603.pdf (Intel IO Controller Hub 8 (ICH8))!?


Last edited by Madis731 on 13 Feb 2008, 10:47; edited 1 time in total
Post 13 Feb 2008, 10:35
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f0dder



Joined: 19 Feb 2004
Posts: 3170
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f0dder
Madis731 wrote:
What I didn't find is how do I code a very primitive example. What are the steps, what is the process...say in 1024x768x32b@60Hz mode put a gray (808080h) pixel at position (3,2)?

Write to the right place in the framebuffer - simple as that.

What's interesting, though, are the steps needed to either switch graphics mode, or query the current graphics mode (including width, height, color depth and pitch... and of course the framebuffer address, we're currently doing a PCI bus scan for it (and that's obviously only for the framebuffer, not the other info)).


Last edited by f0dder on 13 Feb 2008, 10:57; edited 1 time in total
Post 13 Feb 2008, 10:47
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Madis731



Joined: 25 Sep 2003
Posts: 2140
Location: Estonia
Madis731
Quote:

Write to the right place in the framebuffer - simple as that.

I wish it were - I read that there were registers to change the resolution:
Intel docs wrote:

Display Pipeline A
60000h–60003h HTOTAL_A Pipe A Horizontal Total R/W
60004h–60007h HBLANK_A Pipe A Horizontal Blank R/W
60008h–6000Bh HSYNC_A Pipe A Horizontal Sync R/W
6000Ch–6000Fh VTOTAL_A Pipe A Vertical Total R/W
60010h–60013h VBLANK_A Pipe A Vertical Blank R/W
60014h–60017h VSYNC_A Pipe A Vertical Sync R/W

but when I
Code:
mov [60000h],dword 3FFh;1024-1
mov [6000Ch],dword 2FFh; 768-1
    

what should I do next? Reset? I don't think so - with every resolution change. I think there's a COMMIT command somewhere, but where and how to use it?
Post 13 Feb 2008, 10:53
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f0dder



Joined: 19 Feb 2004
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f0dder
Well, getting a pixel plotted is as simple as writing to the framebuffer, but that does obviously require that graphics mode is set Smile

Btw, don't you need to fill out all the 60000h-60014h values? Also I doubt it's as simple as a MOV to that address, it's probably relative to device configuration space?
Post 13 Feb 2008, 10:59
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Madis731



Joined: 25 Sep 2003
Posts: 2140
Location: Estonia
Madis731
from PCI+14h you get the MMADR which is an array. 60000h is just an offset from that. (This is what I understood from VOL1)
Post 13 Feb 2008, 11:21
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f0dder



Joined: 19 Feb 2004
Posts: 3170
Location: Denmark
f0dder
Madis731 wrote:
from PCI+14h you get the MMADR which is an array. 60000h is just an offset from that. (This is what I understood from VOL1)

Yeah, that's what I meant... so you don't "mov [60000h],dword 3FFh;", you "mov [RAX+60000h],dword 3FFh;", with RAX loaded with the linear address mapping for the physical MMADR Smile

(Sorry if I'm nitpicking).

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Post 13 Feb 2008, 11:24
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Madis731



Joined: 25 Sep 2003
Posts: 2140
Location: Estonia
Madis731
I just hope this pondering is getting us somewhere. Actually because MenuetOS still hasn't got ANY graphics drivers, this is a fortunate event that Intel released such documents. I just wish I knew more about it. Don't know where to start from... Sad

EDIT: I will update this post if I find anything...
1) Doesn't help much - the only reference to "display mode"
31760701-Intel G35 Express Chipset.pdf wrote:

10.5.1.3 VESA/VGA Mode
VESA/VGA mode provides compatibility for pre-existing software that set the display
mode using the VGA CRTC registers. Timings are generated based on the VGA register
values and the timing generator registers are not used.

2) VOL_3_display_registers.pdf 2.2 Display Mode Set Sequence -
doesn't explain very clearly, but might be a startingpoint. 6xxxxh 7xxxxh series registers are mentioned.
3) VOL_3_display_registers.pdf 6.6 CRT Controller Register -
tells us only about CRTs, but I don't have them, I can't test them Razz
4) http://xpefiles.com/cs/files/folders/hardware/entry578.aspx
I'm making a very coarse estimation on the closeness of the two graphical cores (945's one and 965's one). If I use only the minimal components of the 965 manual, I won't run into conflicts with 'new features' missing from 945.


Last edited by Madis731 on 14 Feb 2008, 12:51; edited 3 times in total
Post 13 Feb 2008, 11:31
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f0dder



Joined: 19 Feb 2004
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f0dder
Well, please keep reading the documents if you have time (I don't Sad ), any hints and pointers you can find wrt. setting or querying display mode are appreciated!

Sounds likely that there's a COMMIT you need to trigger... I just hope the DMA command buffer stuff mentioned in the documents is only requiered for the more advanced stuff (ie., uploading textures & geometry).
Post 13 Feb 2008, 11:42
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Madis731



Joined: 25 Sep 2003
Posts: 2140
Location: Estonia
Madis731
What I'd like to do is get hardware cursor working for starters.

VOL_3_display_registers.pdf
2.10.2 Cursor A Plane Control Registers
2.10.3.1 CURBCNTR—Cursor B Control Register
6.6.12 CR0A—Text Cursor Start Register
...
Post 13 Feb 2008, 13:40
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