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Index > Heap > SSE, misaligment, timing

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vid
Verbosity in development


Joined: 05 Sep 2003
Posts: 7105
Location: Slovakia
vid
Post 25 Nov 2007, 00:58
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edfed



Joined: 20 Feb 2006
Posts: 4237
Location: 2018
edfed
aïe aïe aïe
(wo)mans who devellop for CONROE & SSE shall read this!
Post 25 Nov 2007, 14:17
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LocoDelAssembly
Your code has a bug


Joined: 06 May 2005
Posts: 4633
Location: Argentina
LocoDelAssembly
Actually (wo)men (this is the correct plural term Wink) who develop for Intel should read that, seems that Intel CPUs was always a shit when an access crosses a cache line and a page boundary.

Quote:
The results were shocking: all Intel chips had the same problem, not just on SSE2 but on all loads back to MMX! Athlons had no penalty for loading across cache lines, and a mere 5% penalty for page lines!
Post 25 Nov 2007, 14:24
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bitRAKE



Joined: 21 Jul 2003
Posts: 2915
Location: [RSP+8*5]
bitRAKE
Isn't this the very reason AMD integrated the memory controller into the CPU? Intel tried to compete by grabbing larger chunks of memory and increasing the cache sizes - that isn't as effective.
Post 25 Nov 2007, 16:17
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