flat assembler
Message board for the users of flat assembler.

Index > Heap > Broken CPU

Author
Thread Post new topic Reply to topic
chaoscode



Joined: 21 Nov 2006
Posts: 64
chaoscode
Hi,
I have a AMD Duron CPU (1,8 GHZ),
CPUID and linux /cat /proc/cpuinfo) says, that my CPU supports SSE.
every time i use a SSE instruction, i will get a illegall instruction opcode.
the instruction is "movups".
i wrote here http://board.flatassembler.net/topic.php?t=920
i think my CPU is broken, amd Wrote:



Quote:
Hello Dennis,

The Duron that you have there should support the full SSE instruction set. You may have a problem with the processor.

If you have a defective processor, and it is a retail boxed version (PIB), you can process an RMA online at our Service Homepage: http://support.amd.com/consumer. If you require additional assistance, please contact your regional AMD Technical Service Center- at the Service Homepage, click on the “Contact Us” tab.



Note: If you have an OEM processor, you will need to contact your vendor for a warranty replacement. AMD will only process warranties for retail boxed processors (PIBs).





Regards,

E####

AMD Technical Service Center



how can i find out, whether my CPU is broken or not?

mfg Dennis
Post 19 Jul 2007, 00:01
View user's profile Send private message ICQ Number Reply with quote
vid
Verbosity in development


Joined: 05 Sep 2003
Posts: 7105
Location: Slovakia
vid
Maybe you could search board for some working SEE examples? I am not sure if there are any, but you can give it a try.

Sorry, i can't help any more, i have never dealt with SSE.
Post 19 Jul 2007, 01:02
View user's profile Send private message Visit poster's website AIM Address MSN Messenger ICQ Number Reply with quote
LocoDelAssembly
Your code has a bug


Joined: 06 May 2005
Posts: 4633
Location: Argentina
LocoDelAssembly
chaoscode, remember what I said in that thread, when I disable SSE on BIOS CPUID still reports that SSE1 is available (but not SSE2 and SSE3) and executing any SSE1 instruction (except for FXSAVE and FXRSTR) produces ilegal instruction exception. However, when I enable it on BIOS SSE1/2/3 are reported by CPUID as available and I don't get any exception.

Also, I posted a quote from an AMD manual claiming that Athlon and Athlon XP processors has SSE disabled BY DEFAULT, and BIOS must enable it. It doesn't mention Duron explicitly but the link to the manual was in the Duron documentation page.
Post 19 Jul 2007, 01:07
View user's profile Send private message Reply with quote
vid
Verbosity in development


Joined: 05 Sep 2003
Posts: 7105
Location: Slovakia
vid
Loco: How does BIOS enable them? Unless there is some locking mechanism like with VMX, you could do maybe enable them yourself.
Post 19 Jul 2007, 01:11
View user's profile Send private message Visit poster's website AIM Address MSN Messenger ICQ Number Reply with quote
LocoDelAssembly
Your code has a bug


Joined: 06 May 2005
Posts: 4633
Location: Argentina
LocoDelAssembly
Unfortunatelly that is what I don't know because I can't find AMD Athlon™ and AMD Duron™ Processor BIOS, Software, and Debug Developers Guide, order#21656.

I know how to do that with Athlon64 because I have Builder's Guide for AMD Athlon™ 64 Processor-Based Desktops and Workstations, but the procedure is uncompatible with older processors.

Surely by replacing the MBR with a code that enables SSE should work, but we need to know how to do that first.

Also, I have not confirmed it but seems that when you enable CR4.OSFXSR CPUID reports SSE available (at least my computer reports SSE as unavailable on boot stage). If CR4.OSFXSR is set then it means that Windows is aware of SSE context saving so writing a driver that enables SSE on the fly could work as well since the OS already saves SSE state. But, again, the AMD's manual or some other information resource must appear to start to do something.
Post 19 Jul 2007, 01:30
View user's profile Send private message Reply with quote
DustWolf



Joined: 26 Jan 2006
Posts: 373
Location: Ljubljana, Slovenia
DustWolf
LocoDelAssembly wrote:
Also, I have not confirmed it but seems that when you enable CR4.OSFXSR CPUID reports SSE available (at least my computer reports SSE as unavailable on boot stage). If CR4.OSFXSR is set then it means that Windows is aware of SSE context saving so writing a driver that enables SSE on the fly could work as well since the OS already saves SSE state. But, again, the AMD's manual or some other information resource must appear to start to do something.


AMD processors also have drivers of their own, so installing one could help solve the problem. I have never attempted to dissasemble one tho, so I am not sure that this is what it does.
Post 19 Jul 2007, 10:10
View user's profile Send private message AIM Address Yahoo Messenger MSN Messenger Reply with quote
revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17278
Location: In your JS exploiting you and your system
revolution
I posted this in another thread: Don't forget that the memory address MUST be 16 byte aligned! Check your code to make sure.
Post 19 Jul 2007, 10:33
View user's profile Send private message Visit poster's website Reply with quote
vid
Verbosity in development


Joined: 05 Sep 2003
Posts: 7105
Location: Slovakia
vid
i think CR4.OSFXSR is explained clearly in Intel Manual:

Quote:
OSFXSR Operating System Support for FXSAVE and FXRSTOR instructions (bit 9 of CR4) — When set, this flag: (1) indicates to software that the oper- ating system supports the use of the FXSAVE and FXRSTOR instructions, (2) enables the FXSAVE and FXRSTOR instructions to save and restore the contents of the XMM and MXCSR registers along with the contents of the x87 FPU and MMX registers, and (3) enables the processor to execute SSE/SSE2/SSE3 instructions, with the exception of the PAUSE, PREFETCHh, SFENCE, LFENCE, MFENCE, MOVNTI, and CLFLUSH.

If this flag is clear, the FXSAVE and FXRSTOR instructions will save and restore the contents of the x87 FPU and MMX instructions, but they may not save and restore the contents of the XMM and MXCSR registers. Also, the processor will generate an invalid opcode exception (#UD) if it attempts to execute any SSE/SSE2/SSE3 instruction, with the exception of PAUSE, PREFETCHh, SFENCE, LFENCE, MFENCE, MOVNTI, and CLFLUSH. The operating system or executive must explicitly set this flag.

CPUID feature flags FXSR, SSE, SSE2, and SSE3 indicate availability of the FXSAVE/FXRESTOR instructions, SSE extensions, SSE2 extensions, and SSE3 extensions respectively. The OSFXSR bit provides operating system software with a means of enabling these features and indicating that the operating system supports the features.
Post 19 Jul 2007, 10:48
View user's profile Send private message Visit poster's website AIM Address MSN Messenger ICQ Number Reply with quote
chaoscode



Joined: 21 Nov 2006
Posts: 64
chaoscode
0x00042000 is aligned^^
i tried it under linux, there it works.
Embarassed

but why don't under win xp sp2?
didnt say anyone, that winxp enables it?
where can i get some drivers for my duron, i cant find some one from AMD

mfg Dennis
Post 19 Jul 2007, 14:01
View user's profile Send private message ICQ Number Reply with quote
f0dder



Joined: 19 Feb 2004
Posts: 3170
Location: Denmark
f0dder
Imho if your processor was broken, you'd have a lot more serious problems than just SSE not working... can you isolate as little code as possible that shows the problem and post .asm+.exe here in a zip file?
Post 20 Jul 2007, 10:52
View user's profile Send private message Visit poster's website Reply with quote
OzzY



Joined: 19 Sep 2003
Posts: 1029
Location: Everywhere
OzzY
Interesting thing.
Is it possible to test if a 64bit dual core machine is really supporting dual core and the instructions it's suposed to support?
Post 20 Jul 2007, 12:21
View user's profile Send private message Reply with quote
f0dder



Joined: 19 Feb 2004
Posts: 3170
Location: Denmark
f0dder
Get zcpu, wcpu or whatever it's called and check what it reports? Then, write tests? Smile

_________________
Image - carpe noctem
Post 20 Jul 2007, 14:38
View user's profile Send private message Visit poster's website Reply with quote
chaoscode



Joined: 21 Nov 2006
Posts: 64
chaoscode
hi,
i tried it,
i noticed something wrong,
When i used Ollydbg, he always said movaps.
after creatign some testapplications, i feel bad, because there works sse.
I Compared the instructions in ollydbg, and noticed, that the opcode where the #UD occurs had a prefix. ->0x66
i looked in the source and saw my mistake, it was movupd, a sse2 instruction, not supported by my CPU

sorry,
*in die ecke stell und schäm*
Post 20 Jul 2007, 16:16
View user's profile Send private message ICQ Number Reply with quote
rugxulo



Joined: 09 Aug 2005
Posts: 2341
Location: Usono (aka, USA)
rugxulo
chaoscode wrote:

I Compared the instructions in ollydbg, and noticed, that the opcode where the #UD occurs had a prefix. ->0x66
i looked in the source and saw my mistake, it was movupd, a sse2 instruction, not supported by my CPU


This is just one more symptom of FASM not having [cpu 8086] like NASM / YASM does. (Granted, I can understand that Tomasz is very busy and can't be expected to do everything, but man, we could sure use that feature.)

In deference to that, you have to do one of the following:


  • use BIEW, which colors the disassembly according to processor
  • use NASM / YASM instead (or in tandem, comparing code output)
  • write FASM macros to prevent such errors (e.g. MCD's ONLY8086.INC)
Post 20 Jul 2007, 20:55
View user's profile Send private message Visit poster's website Reply with quote
chaoscode



Joined: 21 Nov 2006
Posts: 64
chaoscode
Quote:

This is just one more symptom of FASM not having [cpu 8086] like NASM / YASM does


sorry, i don't understand.

i wrote in the source movupd.
Ollydgb sayd that that is a movups with a prefix

the opcode is rigth,
just the dissassembly by ollydbg is wrong..

fasm is ok, or what did you mean?

ps:
what is [cpu8086]???
Post 20 Jul 2007, 22:12
View user's profile Send private message ICQ Number Reply with quote
f0dder



Joined: 19 Feb 2004
Posts: 3170
Location: Denmark
f0dder
Using a "CPU xxx" statement limits the instructions that the assembler will accept, warning that "this instruction is not supported for target cpu type".

OllyDebug showing wrong disassembly is because OllyDebug hasn't been updated for a while, and new processors have appeared.
Post 20 Jul 2007, 22:24
View user's profile Send private message Visit poster's website Reply with quote
chaoscode



Joined: 21 Nov 2006
Posts: 64
chaoscode
thx

SSE2?
not supoerted?
so long not updated?
Is ollydgb Dead?
i think he's working for version 2.0,
or isn't he?

mfg Dennis
Post 20 Jul 2007, 22:42
View user's profile Send private message ICQ Number Reply with quote
f0dder



Joined: 19 Feb 2004
Posts: 3170
Location: Denmark
f0dder
Last update to OllyDebug 1.x was end of May 2004... so yeah, it's been a while since it was updated. Oleh is working on 2.0, but he's been working on it for quite a while, and it's a complete rewrite, so...
Post 20 Jul 2007, 22:49
View user's profile Send private message Visit poster's website Reply with quote
LocoDelAssembly
Your code has a bug


Joined: 06 May 2005
Posts: 4633
Location: Argentina
LocoDelAssembly
Quote:
This is just one more symptom of FASM not having [cpu 8086] like NASM / YASM does. (Granted, I can understand that Tomasz is very busy and can't be expected to do everything, but man, we could sure use that feature.)


For that reason revolution provided to us his excelent macroses
http://board.flatassembler.net/topic.php?t=6921
Post 20 Jul 2007, 23:15
View user's profile Send private message Reply with quote
Display posts from previous:
Post new topic Reply to topic

Jump to:  


< Last Thread | Next Thread >
Forum Rules:
You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot vote in polls in this forum
You can attach files in this forum
You can download files in this forum


Copyright © 1999-2020, Tomasz Grysztar.

Powered by rwasa.