Message board for the users of flat assembler.
> Main > AMD MOESI protocol, cache overlap?
AMD vol2 7.2 talks about the MOESI cache coherency protocol
M = modified, notequals main mem, unshared
O = owned, notequals main mem,
E = exclusive, = main mem, unshared
S = shared, = main mem,
I = invalid,
say caching is fully on, ie write back caching, + read caching,
now if a cpu READS some memory say at address xyz
which may or may not be in other cpus caches,
immediately afterwards will xyz be in the cpus private caches?
if CPU B has address uvw in its caches,
now CPU A writes to address uvw I think now that
CPU A will have uvw in the owned state,
will uvw be now invalid in B's cache?
and now say B reads uvw,
will this now be in the shared state?
also MOESI appears to be saying that uvw now
will be written to main memory?
does this mean that whenever memory is in several
caches it will also always be coherent with main memory?
if a cpu reads data in another cpus write cache then
the data gets written to main memory and is now
in both read caches?
why dont they allow caches to share memory which isnt
coherent with main memory, ie main memory is stale?
the AMD docs say about Owned: on p199
"only one processor can hold the data in the owned state-
all other processors must hold the data in the shared state"
is that wrong?
my interpretation is that if one processor holds the mem in the
owned state then the other cpus CANNOT hold the data so
the data cannot be in the other cpus caches??
the quote appears to be saying the memory is in the one CPU
as owned and in the others as shared, but the docs say
shared mem is the same as main mem, which contradicts
the fact it is owned for the one cpu which means it isnt
the same as main mem,
one thing I want to know is whether for Intel and AMD that
if a cpu A reads something which isnt in its caches but is in
other cpus caches (eg B, C, D) does that data afterwards end up in
the cpu A's caches, or does A have to snoop the data each time?
|05 Jul 2007, 20:24||
That's pretty interesting, I think this issue is why processors are moving to a shared L3 cache architecture, so that a block of memory need only be consistant in the L3 cache even if more than one core is working on it.
|08 Jul 2007, 02:00||
Shared cache (if done right) will also be better for performance in some cases, since shared structures are (duh! ) shared, leaving more room to cache other stuff.
|08 Jul 2007, 18:15||
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