4kB page from RAM into L2?)

No, only cache line size which can be 16, 32 or 64 bytes depending of the CPU.

(...) The minimum unit of data used when interacting with the memory is not a 32-byte burst cycle; rather, it's an entire page. The delays that occur when accessing the page for the first time are slightly smaller than the time required to read the entire page. This means that, no matter how many bytes of the page are read, processing takes the same time amount as if it were read as a whole. (...)

(...) When accessing the page for the first time, the processor reads these data from the physical memory into its internal buffer, the Translation Look-aside Buffer (TLB). All further attempts to access the same page occur without delays until this information is removed from the TLB. (...)

5.5 Translation-Lookaside Buffer (TLB)
When paging is enabled, every memory access has its virtual address automatically translated into a
physical address using the page-translation hierarchy. Translation-lookaside buffers (TLBs), also
known as page-translation caches, nearly eliminate the performance penalty associated with page
translation. TLBs are special on-chip caches that hold the most-recently used virtual-to-physical
address translations. Each memory reference (instruction and data) is checked by the TLB. If the
translation is present in the TLB, it is immediately provided to the processor, thus avoiding external
memory references for accessing page tables.
TLBs take advantage of the principle of locality. That is, if a memory address is referenced, it is likely
that nearby memory addresses will be referenced in the near future. In the context of paging, the
proximity of memory addresses required for locality can be broad—it is equal to the page size. Thus, it
is possible for a large number of addresses to be translated by a small number of page translations. This
high degree of locality means that almost all translations are performed using the on-chip TLBs.

                        actual = 1;
                        do {
                                actual = tab[actual];   
                        } while (actual != 0);    

again:  mov  eax, [405060 + eax*4]
        test eax, eax
        jnz  again
    

I'm filling the table with random values from 1 to N-1 (but there are no two elements of tab with the same value! AND tab[i] != i for all i < N). Only the last element of tab has "0".

You forgot to specify the memory speed but supposing your memory has a latency of 100 ns (Everest shows that latency for a Pentium M730J 1600 MHz Dual DDR2-400), it means the CPU waits 1.6*100 = 160 cycles to get access to data.

Try using VirtualAlloc with PAGE_NOCACHE to see what happens.

;try either...
again:
        mov     eax, [tab + eax*4]
        test     eax, eax
        prefetch1/2/nta [eax]
        jnz     again

;...or this one
again:
        mov     eax, [tab + eax*4]
        prefetch1/2/nta [eax]
        test     eax, eax
        jnz     again
    

;consider tab to be an array of n-ints
;doActionX all do something with the passed value

;not so fast
int i;
for(i=0; i<n; i++){ doAction1(&tab[i]); }
for(i=0; i<n; i++){ doAction2(&tab[i]); }
for(i=0; i<n; i++){ doAction3(&tab[i]); }

;faster
int i;
for(i=0; i<n; i++){
  doAction1(&tab[i]);
  doAction2(&tab[i]);
  doAction3(&tab[i]);
}