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weiss



Joined: 03 Jan 2006
Posts: 25
weiss
i was using version 1.65 for this assembly, so if the issue has been since resolved in latest release, i apologise for post.
i don't have internet access from home to check much info.

i think there might be problem with the parser for 64-bit instructions,
correct me if i'm wrong.

here is 32-bit indexing instruction

Code:
   mov  eax,[eax+4*ecx]    


if i want to use the extended registers in 64-bit, like:

Code:
   mov  eax,dword[r12+4*r10]    


this is ok, but if i want to do the following.

Code:
   movzx  eax,word [edx+2*r12d-2]    


fasm complains with the error:

movzx eax,word [edx+2*r12d-2]
error: reserved word used as symbol.

fasm doesn't seem to recognise r8d - r15d
as valid 32-bit registers in this kind of addressing.

if i change edx to rdx & r12d to r12, the instruction
succeeds, but using edx & r12d is a legal instruction.

another thing is when comparing 64-bit values.

cmp qword [rsi+rax], 1234567812345678h
error: value out of range.

is it not possible to compare 64-bit values?
if not, can someone explain WHY?

also, why does an instruction like XOR ECX,ECX zero extend RCX?
32-bit ROL/ROR don't work this way, so why should 32-bit XORs,SUBs,ADDs..etc..
doesn't make much sense!!

is this maybe a bug in the cpu driver?
take this for example:

Code:
   or   rcx,-1            ; set rcx to 0ffffffffffffffffh
   inc  ecx               ; set rcx to 00000000000000000h
   dec  ecx               ; set rcx to 000000000ffffffffh    

see what i mean?
how can an INC ECX set 64-bits, but a DEC ECX set
only 32-bits????
this has gotta be wrong!!

i was tryin to write this tcp application in 64-bit asm.
the error is below.
anyone have a solution?

Code:
; - - - - - - - - - - - - - - - - - - - - - -
;tcp.asm [50]:
;   mov  word[rdx+sin.sin_port],ax
;error: undefined symbol.
;
; tcp.asm
;
format PE64 console 4.0
entry entrypoint

PORT   equ   80

struc WSADATA
{
   wVersion       dw   ?
   wHighVersion   dw   ?
   iMaxSockets    dw   ?
   iMaxUdpDg      dw   ?
   lpVendorInfo   dq   ?
   szDescription  db   256+1 dup (?)
   szSystemStatus db   128+1 dup (?)
   _padding       db   6     dup (?)
}

struc SOCKADDR_IN
{
   sin_family      dw ?
   sin_port        dw ?
   ;sin_addr        in_addr ?
   sin_addr        db 4 dup(?)
   sin_zero        db 8 dup(?)
}

section '.data' code readable writeable

wsaData WSADATA
sin SOCKADDR_IN

section '.text' code readable writeable executable

entrypoint:
   int3

   lea  rdx,[wsaData]
   mov  cx,2
   call  qword[WSAStartup]
   test  rax,rax
   jnz  exit_tcp

   mov ax,PORT
   xchg al,ah
   lea  rdx,[sin]
   mov  word[rdx+sin.sin_port],ax           ; error here

   ; other code omitted..

   call  qword[WSACleanup]
exit_tcp:
   xor rcx,rcx
   call  qword[ExitProcess]
   
section '.idata' import data readable writeable

  dd 0,0,0,RVA kernel_name,RVA kernel_table
  dd 0,0,0,RVA ws2_32_name,RVA ws2_32_table
  dd 0,0,0,0,0

  kernel_table:
    ExitProcess dq RVA _ExitProcess
    dq 0
    
  ws2_32_table:
    WSAStartup dq RVA _WSAStartup
    WSASocketA dq RVA _WSASocketA
    connect    dq RVA _connect
    dq 0

  kernel_name db 'KERNEL32.DLL',0
  ws2_32_name db 'WS2_32.DLL',0

  _ExitProcess dw 0
    db 'ExitProcess',0
    
  _WSAStartup dw 0
    db 'WSAStartup',0
  _WSACleanup dw 0
    db 'WSACleanup',0
  _WSASocketA dw 0
    db 'WSASocketA',0
  _connect    dw 0
    db 'connect',0
    
; - - - - - - - - - - - - - - - - - - - - - - - - - -    
Post 02 Aug 2006, 09:25
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Tomasz Grysztar



Joined: 16 Jun 2003
Posts: 7734
Location: Kraków, Poland
Tomasz Grysztar
weiss wrote:
fasm doesn't seem to recognise r8d - r15d
as valid 32-bit registers in this kind of addressing.

This was fixed in 1.66

weiss wrote:
cmp qword [rsi+rax], 1234567812345678h
error: value out of range.

is it not possible to compare 64-bit values?
if not, can someone explain WHY?

The long mode instructions generally use simm32 in encoding, so you can use only 32-bit signed immediates that are sign-extended into 64 bits when executing the instruction. The only exception is the special case of MOV instruction, the "mov r64,imm64" form.
So to compare a fully-qualified 64-bit values you have to do it like:
Code:
mov rbx,1234567812345678h
cmp qword [rsi+rax],rbx    


weiss wrote:
lso, why does an instruction like XOR ECX,ECX zero extend RCX?
32-bit ROL/ROR don't work this way, so why should 32-bit XORs,SUBs,ADDs..etc..

In AMD64/EM64T architectures any instruction that targets the 32-bit register, clears the upper 32 bit of the 64-bit register that contains it. This is a general rule, even the "xchg eax,eax" will clear the upper 32 bits of RAX register.

I highly recommend spending some time on reading the AMD64 architecture manuals.
Post 02 Aug 2006, 09:41
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weiss



Joined: 03 Jan 2006
Posts: 25
weiss
ok, Thomasz, sorry for silly questions,again.
thanks!
Post 02 Aug 2006, 10:45
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