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Hunter



Joined: 07 Jun 2006
Posts: 41
Hunter
Will FASM support AMD virtualization instructions (see AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions) ?
Post 13 Jun 2006, 12:33
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Tomasz Grysztar
Assembly Artist


Joined: 16 Jun 2003
Posts: 7723
Location: Kraków, Poland
Tomasz Grysztar
fasm is willing to support any extensions of IA32/AMD64/EM64T architectures that Intel and/or AMD implements.
Post 13 Jun 2006, 12:59
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Hunter



Joined: 07 Jun 2006
Posts: 41
Hunter
ok, and when will fasm support this extension? Smile
Post 13 Jun 2006, 13:37
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quasar



Joined: 09 Oct 2005
Posts: 16
quasar
Send 1000$ to Tomasz and you will have it tomorrow Very Happy
Post 13 Jun 2006, 14:58
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tom tobias



Joined: 09 Sep 2003
Posts: 1320
Location: usa
tom tobias
are you sure? have you some experience with that method? Cool
Post 13 Jun 2006, 15:59
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quiveror



Joined: 20 Jun 2003
Posts: 34
quiveror
That's what macros are for.
Post 13 Jun 2006, 16:56
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vid
Verbosity in development


Joined: 05 Sep 2003
Posts: 7105
Location: Slovakia
vid
you don't need to send money, it's enough to convice him with arguments Smile

and i do have some experience with THIS method Wink
Post 13 Jun 2006, 18:29
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peter



Joined: 09 May 2006
Posts: 63
peter
Code:
macro vmrun   {db 0x0F, 0x01, 0xD8}
macro vmcall  {db 0x0F, 0x01, 0xD9}
macro vmload  {db 0x0F, 0x01, 0xDA}
macro vmsave  {db 0x0F, 0x01, 0xDB}
macro stgi    {db 0x0F, 0x01, 0xDC}
macro clgi    {db 0x0F, 0x01, 0xDD}
macro skinit  {db 0x0F, 0x01, 0xDE}
macro invlpga {db 0x0F, 0x01, 0xDF}
macro mov x, y {
    ; for 32-bit mode and AMD processors only
    if x eq cr8 & y in <eax, ebx, ecx, edx, ebp, esp, esi, edi>
        lock mov cr0, y
    else if y eq cr8 & x in <eax, ebx, ecx, edx, ebp, esp, esi, edi>
        lock mov x, cr0
    ; an attempt to do the same thing in 64-bit mode
    ;if x eq cr8 & y in <eax, ebx, ecx, edx, ebp, esp, esi, edi>
    ;   db 0x44 ; REX.R
    ;   mov cr0, y
    ;else if y eq cr8 & x in <eax, ebx, ecx, edx, ebp, esp, esi, edi>
    ;   db 0x44 ; REX.R
    ;   mov x, cr0
    else
       mov x, y
    end if
}    

But I haven't test it, because I have no processor with Pacifica support Sad.
Post 14 Jun 2006, 05:26
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Madis731



Joined: 25 Sep 2003
Posts: 2141
Location: Estonia
Madis731
When we already are on the subject on Intel's virtualization then I've got a question. What is it used for? I've heard sad news that its only *really* useful to emulators and such Sad ...is it true?

Intel only mentions it has such a thing, but not real-world examples Razz just like with pretty much everything Smile
Post 14 Jun 2006, 16:51
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Hunter



Joined: 07 Jun 2006
Posts: 41
Hunter
The real-world example is VmWare. They are using these extensions.
http://www.vmware.com/products/gsx/
Post 15 Jun 2006, 09:01
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HyperVista



Joined: 18 Apr 2005
Posts: 691
Location: Virginia, USA
HyperVista
@Madis731 - Intel and AMD have provided support for virtualization in silicon and extended the IA32 instruction set as part of their contribution to the Trusted Computing Group's (TCG - www.trustedcomputinggroup.org) Trusted Computing Base (TCB).

The goal is to provide code and process isloation via virtual machines.

Current virtualization technology (VMWare, Virtual PC, Bochs, etc.) have to trap and perform binary translation on certain privileged calls that can't be virtualized (because they don't create page faults when they should). They have to perform what is known as ring compression or ring aliasing to "trick" the guest OS image in to believing it is actually running in the classic ring0 and ring3 architecture when it is actually running ring1 and ring3 and all calls to ring0 are trapped, passed to the real ring0 and responses passed back up to the calling guest OS. This creates quite a performance hit.

These new chips from Intel and AMD provide true mulitple ring0 and ring3 instances, eliminating the need for all that binary translation and ring aliasing work. The virtual machines on these processors will run as fast as native OSes... no lag from the virtual environment we have today.

It is important for all of us to fully understand the these new virtualization extensions because they will form the foundation of many security applications of the near future. We will need to determine if the CPU is VT-x compliant and go from there.
Post 16 Jun 2006, 18:02
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Tomasz Grysztar
Assembly Artist


Joined: 16 Jun 2003
Posts: 7723
Location: Kraków, Poland
Tomasz Grysztar
The AMD manuals when describing instructions like VMLOAD and INVLPGA say that "the portion of RAX used to form the address is determined by the
effective address size". I assumed this needs the 67h prefix works here and I implemented it this way. It would be nice if someone with access to such hardware could test it and confirm.
Post 30 Jun 2006, 21:22
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HyperVista



Joined: 18 Apr 2005
Posts: 691
Location: Virginia, USA
HyperVista
Tomasz, I'll try to test it out next week. I'm traveling now and will return to my lab facilities early next week.
Post 01 Jul 2006, 02:19
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Hunter



Joined: 07 Jun 2006
Posts: 41
Hunter
Maybe, the right mnemocode for instructions like AMD VMLOAD, VMRUN and etc. must use [RAX] and [EAX], because "the portion of RAX used to form the address is determined by the effective address size" ?
for examlpe:
VMRUN [RAX]
VMLOAD [EAX]
Post 24 Jul 2006, 09:07
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Hunter



Joined: 07 Jun 2006
Posts: 41
Hunter
Tomasz, What do you think about this suggestion? Smile
Post 16 Aug 2006, 09:17
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Tomasz Grysztar
Assembly Artist


Joined: 16 Jun 2003
Posts: 7723
Location: Kraków, Poland
Tomasz Grysztar
There's no reason to use non-standard syntax here.
Post 16 Aug 2006, 22:08
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Hunter



Joined: 07 Jun 2006
Posts: 41
Hunter
Ok, I'll try to explain my opinion Smile. AMD uses following mnemonics: instruction_name reg/mem
and VMRUN RAX can mean: VMRUN "memory, which is addressed through RAX only"
And AMD uses 67h prefix to determine the effective address size for VMLOAD, VMRUN and etc.
Post 17 Aug 2006, 12:40
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f0dder



Joined: 19 Feb 2004
Posts: 3170
Location: Denmark
f0dder
By the way, vmware claims that the current implementation of the VMX is slower than software emulation in some circumstances...
Post 18 Aug 2006, 10:40
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Hunter



Joined: 07 Jun 2006
Posts: 41
Hunter
VT-x is greatly optimized for Intel Core and Intel Core 2 in comparision with Pentium 4 D 9xx.
Post 18 Aug 2006, 15:36
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