Will FASM support AMD virtualization instructions (see AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions) ?

fasm is willing to support any extensions of IA32/AMD64/EM64T architectures that Intel and/or AMD implements.

ok, and when will fasm support this extension?

Send 1000$ to Tomasz and you will have it tomorrow

are you sure? have you some experience with that method?

That's what macros are for.

you don't need to send money, it's enough to convice him with arguments

and i do have some experience with THIS method

But I haven't test it, because I have no processor with Pacifica support .

When we already are on the subject on Intel's virtualization then I've got a question. What is it used for? I've heard sad news that its only *really* useful to emulators and such ...is it true?

Intel only mentions it has such a thing, but not real-world examples just like with pretty much everything

The real-world example is VmWare. They are using these extensions.
http://www.vmware.com/products/gsx/

@Madis731 - Intel and AMD have provided support for virtualization in silicon and extended the IA32 instruction set as part of their contribution to the Trusted Computing Group's (TCG - www.trustedcomputinggroup.org) Trusted Computing Base (TCB).

The goal is to provide code and process isloation via virtual machines.

Current virtualization technology (VMWare, Virtual PC, Bochs, etc.) have to trap and perform binary translation on certain privileged calls that can't be virtualized (because they don't create page faults when they should). They have to perform what is known as ring compression or ring aliasing to "trick" the guest OS image in to believing it is actually running in the classic ring0 and ring3 architecture when it is actually running ring1 and ring3 and all calls to ring0 are trapped, passed to the real ring0 and responses passed back up to the calling guest OS. This creates quite a performance hit.

These new chips from Intel and AMD provide true mulitple ring0 and ring3 instances, eliminating the need for all that binary translation and ring aliasing work. The virtual machines on these processors will run as fast as native OSes... no lag from the virtual environment we have today.

It is important for all of us to fully understand the these new virtualization extensions because they will form the foundation of many security applications of the near future. We will need to determine if the CPU is VT-x compliant and go from there.

The AMD manuals when describing instructions like VMLOAD and INVLPGA say that "the portion of RAX used to form the address is determined by the
effective address size". I assumed this needs the 67h prefix works here and I implemented it this way. It would be nice if someone with access to such hardware could test it and confirm.

Tomasz, I'll try to test it out next week. I'm traveling now and will return to my lab facilities early next week.

Maybe, the right mnemocode for instructions like AMD VMLOAD, VMRUN and etc. must use [RAX] and [EAX], because "the portion of RAX used to form the address is determined by the effective address size" ?
for examlpe:
VMRUN [RAX]
VMLOAD [EAX]

Tomasz, What do you think about this suggestion?

There's no reason to use non-standard syntax here.

Ok, I'll try to explain my opinion . AMD uses following mnemonics: instruction_name reg/mem
and VMRUN RAX can mean: VMRUN "memory, which is addressed through RAX only"
And AMD uses 67h prefix to determine the effective address size for VMLOAD, VMRUN and etc.

By the way, vmware claims that the current implementation of the VMX is slower than software emulation in some circumstances...

VT-x is greatly optimized for Intel Core and Intel Core 2 in comparision with Pentium 4 D 9xx.