Why fasm gives out a mistake on a design add eax, [edx+esi+edi]?

You can check your instruction set documentation.

There's no opcode add reg, [reg1 + reg2 + reg3]
So you'll have to

lea ecx, [esi + edx]
add eax, [edi + ecx]

even better

shoorick, why is your solution better than r22's?

in true there is no difference in bytes (do not know about clocks), but usually i try to approach to shema:
addr = [indexing register]+[common register]+[offset]
for example, in 16-bit mode this is possible:
add ax,[di + cx]
and this no:
add ax,[dx + cx]
so, it is just a rule

Yeah, I got it.

Just one thing, [di+cx] addressing in not applicable in 16-bit mode, only [di+bx] or [di+bp].

he is correct

you are right. i see, 16-bit ages are leaving me more and more