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Borsuc



Joined: 29 Dec 2005
Posts: 2466
Location: Bucharest, Romania
Borsuc
yes.. real mode actually uses GDT, LDT too, but it's hidden.. and every time you set up a register, it's actually updated in those tables (hidden), right? I mean, the base is set as segment*16, but the limit is not modified (Intel claims it's reset, but THAT IS NOT TRUE), so modifying the limit to 4GB will actually let you use 32-bit register adressing in real mode, thus:

Code:
mov ax, [ebx]    


that's why you need to enter Pmode first -> set up the limit in the tables, then switch back to Real mode, and let the limit to 4GB, so the access is allowed. Smile
Post 25 Jan 2006, 22:10
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vid
Verbosity in development


Joined: 05 Sep 2003
Posts: 7105
Location: Slovakia
vid
right
Post 25 Jan 2006, 22:26
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a16b03



Joined: 24 Jan 2006
Posts: 43
Location: Riga, Latvia
a16b03
Your right The_Grey_Beast

But what can you tell about this

P6 can address 0 to 2^36-1 = 64Gb Question
HOW???



P.S.
I'm going to take a 48h sleep
Post 26 Jan 2006, 00:25
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Borsuc



Joined: 29 Dec 2005
Posts: 2466
Location: Bucharest, Romania
Borsuc
a16b03 wrote:
P6 can address 0 to 2^36-1 = 64Gb Question

Well, I'm not really experienced with this, but I think it has to do with the fact that ONLY the OFFSET is 32-bits, so you can still have 'selectors'. Basically, I think the 4GB limit is PER PROCESS (or application), but the entire virtual memory is actually much bigger.

Sure, using selectors and 4GB offsets yields MUCH HIGHER virtual addressing, but P6 has only 36-bit address bus, so it can only address 64GB...

I think this only goes for paging anyways, I don't think you can do this in Flat Real Mode, though. Maybe someone else can explain it better? Smile
Post 26 Jan 2006, 18:35
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MazeGen



Joined: 06 Oct 2003
Posts: 975
Location: Czechoslovakia
MazeGen
a16b03 wrote:

But what can you tell about this

P6 can address 0 to 2^36-1 = 64Gb Question
HOW???

It is called PAE paging mechanism:
Intel System Programming Manual wrote:

3.8 36-BIT PHYSICAL ADDRESSING USING THE PAE PAGING
MECHANISM
The PAE paging mechanism and support for 36-bit physical addressing were introduced into the
IA-32 architecture in the Pentium Pro processors.

When the PAE paging mechanism is enabled, the processor supports two sizes of pages:
4-KByte and 2-MByte. As with 32-bit addressing, both page sizes can be addressed within the
same set of paging tables (that is, a page-directory entry can point to either a 2-MByte page or
a page table that in turn points to 4-KByte pages). To support the 36-bit physical addresses, the
following changes are made to the paging data structures:
• The paging table entries are increased to 64 bits to accommodate 36-bit base physical
addresses. Each 4-KByte page directory and page table can thus have up to 512 entries.
• A new table, called the page-directory-pointer table, is added to the linear-address
translation hierarchy. This table has 4 entries of 64-bits each, and it lies above the page
directory in the hierarchy. With the physical address extension mechanism enabled, the
processor supports up to 4 page directories.
• The 20-bit page-directory base address field in register CR3 (PDBR) is replaced with a
27-bit page-directory-pointer-table base address field. The updated field provides the 27
most-significant bits of the physical address of the first byte of the page-directory pointer
table (forcing the table to be located on a 32-byte boundary).
Since CR3 now contains the page-directory-pointer-table base address, it can be referred to
as the page-directory-pointer-table register (PDPTR). See Figure 3-17.
• Linear address translation is changed to allow mapping 32-bit linear addresses into the
larger physical address space.
Post 27 Jan 2006, 09:49
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a16b03



Joined: 24 Jan 2006
Posts: 43
Location: Riga, Latvia
a16b03
Thanks to all for info...
Post 31 Jan 2006, 20:22
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