mov ax, [ebx]    

P6 can address 0 to 2^36-1 = 64Gb

But what can you tell about this

P6 can address 0 to 2^36-1 = 64Gb
HOW???

3.8 36-BIT PHYSICAL ADDRESSING USING THE PAE PAGING
MECHANISM
The PAE paging mechanism and support for 36-bit physical addressing were introduced into the
IA-32 architecture in the Pentium Pro processors.

When the PAE paging mechanism is enabled, the processor supports two sizes of pages:
4-KByte and 2-MByte. As with 32-bit addressing, both page sizes can be addressed within the
same set of paging tables (that is, a page-directory entry can point to either a 2-MByte page or
a page table that in turn points to 4-KByte pages). To support the 36-bit physical addresses, the
following changes are made to the paging data structures:
• The paging table entries are increased to 64 bits to accommodate 36-bit base physical
addresses. Each 4-KByte page directory and page table can thus have up to 512 entries.
• A new table, called the page-directory-pointer table, is added to the linear-address
translation hierarchy. This table has 4 entries of 64-bits each, and it lies above the page
directory in the hierarchy. With the physical address extension mechanism enabled, the
processor supports up to 4 page directories.
• The 20-bit page-directory base address field in register CR3 (PDBR) is replaced with a
27-bit page-directory-pointer-table base address field. The updated field provides the 27
most-significant bits of the physical address of the first byte of the page-directory pointer
table (forcing the table to be located on a 32-byte boundary).
Since CR3 now contains the page-directory-pointer-table base address, it can be referred to
as the page-directory-pointer-table register (PDPTR). See Figure 3-17.
• Linear address translation is changed to allow mapping 32-bit linear addresses into the
larger physical address space.