flat assembler
Message board for the users of flat assembler.
Index
> Non-x86 architectures > FASMARM v1.44 - Cross assembler for ARM CPUs Goto page Previous 1, 2, 3 ... 30, 31, 32, 33 Next |
Author |
|
revolution 23 Dec 2018, 17:13
There are currently no plans to rewrite fasmarm in native ARM code.
So to run fasmarm, or fasm for that matter, on a tablet or phone you will need an 80386 emulator/VM. To run the IDE you will also need a windows VM or have WINE running also. |
|||
23 Dec 2018, 17:13 |
|
guignol 29 Dec 2018, 13:46
and no muscle, i get it
_________________ qiq; |
|||
29 Dec 2018, 13:46 |
|
TmEE 19 Jun 2019, 22:33
Allo !
I have been using FASMARM for STM32 development for a little while and I have found a bug regarding immediate offset handling. FASMARM allows the more conventional syntax of [Rx+123] instead of [Rx,123] that is standard in ARM and I have been using it instead but I have found out that if you use the offset in hexadecimal (using $) the instruction will not always assemble with correct offset. LDR R0, [R8+$12] produced offset equivalent of $18 in some tests I was performing. LDR R0, [R8,$12] gives correct result. I have converted all my code to use the conventional ARM syntax but it would be nice if this could be looked at and perhaps fixed or maybe opposite and disallowed entirely. I cannot say I'm a big fan of the ARM syntax, especially with 68K background where similar operations use more intuitive representation. |
|||
19 Jun 2019, 22:33 |
|
revolution 19 Jun 2019, 22:54
Yes, you are right. And it appears to only affect thumb mode long form instructions using high registers.
Code: ldr r0,[r8+$12] thumb ldr r0,[r8+$12] ldr r0,[r0+$12] ldr r0,[r0+$10] Code: 00000000: E5980012 V1 ldr r0,[r8,0x12] thumb 00000008: F8D8001A 7M ldr r0,[r8,0x1A] ;Oops 0000000C: F8D00012 7M ldr r0,[r0,0x12] 00000010: 6900 V4T ldr r0,[r0,0x10] |
|||
19 Jun 2019, 22:54 |
|
guignol 20 Jun 2019, 03:12
revolution wrote: And it appears to only affect thumb mode long form instructions using high registers. |
|||
20 Jun 2019, 03:12 |
|
TmEE 20 Jun 2019, 12:49
Thänk you for the quick look at the matter, I look forward to any developments ~
EDIT: I am wondering if there's a better way to define interrupt vectors (or other addresses) than to do DW Label+1 ? Lowest bit needs to be set as I found out or the CPU will hard fault. Perhaps there could be dedicated data definition like say DV (define vector) which automatically sets the lowest bit ? |
|||
20 Jun 2019, 12:49 |
|
TmEE 24 Sep 2019, 16:33
Looks like this has fallen into cracks lol (I'm not in actual hurry, I only now remembered to check up on this)
|
|||
24 Sep 2019, 16:33 |
|
revolution 24 Sep 2019, 23:24
Yeah, I thought some time back that it would be a week till I got back to my dev system. But the 737MAX thing has turned into a really big problem. I should refrain from predicting an end time. As it looks now it might be never. Sigh.
For your suggestion of DV (which I only saw now). You can use a macro to do the CPU specific requirements. It isn't part of the instruction set so I think making special assembler directives isn't the proper place to have it. Code: macro DV pointer { dw pointer + 1 } |
|||
24 Sep 2019, 23:24 |
|
murder 02 Nov 2019, 16:14
Is it planned to add support for the ELF64? It`s need for Android programming.
|
|||
02 Nov 2019, 16:14 |
|
revolution 02 Nov 2019, 16:20
murder wrote: Is it planned to add support for the ELF64? |
|||
02 Nov 2019, 16:20 |
|
guignol 02 Nov 2019, 19:33
woo-ooh !
|
|||
02 Nov 2019, 19:33 |
|
guignol 02 Nov 2019, 20:52
You know, I think Boeing should release all of its software opensource
|
|||
02 Nov 2019, 20:52 |
|
ProMiNick 02 Nov 2019, 23:19
revolution, if thou going back to dev system please cut off optimization mov ->unpaired movw (unpaired with movt) - reason relocations respect only movw movt pair.
|
|||
02 Nov 2019, 23:19 |
|
revolution 03 Nov 2019, 03:28
ProMiNick wrote: revolution, if thou going back to dev system please cut off optimization mov ->unpaired movw (unpaired with movt) - reason relocations respect only movw movt pair. |
|||
03 Nov 2019, 03:28 |
|
MazeGen 23 Nov 2019, 22:13
revolution wrote:
Wait guys... so this is not supposed to work on Android? Code: format ELF64 executable processor cpu64_v8 entry start segment readable executable start: mov x0, 1 adr x1, msg mov x2, msg_len mov x8, 4 svc 0 mov x0, 0 mov x8, 1 svc 0 msg DB "hello from arm64", 10 msg_len=$-msg EDIT: wow, this generates ELF x64 without any errors |
|||
23 Nov 2019, 22:13 |
|
guignol 24 Nov 2019, 06:08
Czechoslovakia, anyone?
|
|||
24 Nov 2019, 06:08 |
|
murder 01 Dec 2019, 05:59
MazeGen
It will generate x64 ELF. For ARM64 need to be replace e_machine with EM_AARCH64 and e_flags must be equal to 5000000h. Also if you want to use dynamik linking e_type field must be ET_DYN. |
|||
01 Dec 2019, 05:59 |
|
murder 01 Dec 2019, 06:04
revolution
If try to compile this code in FASMARM 1.43 - it will be crashed Code: if 0<>0 [a->b] ;if remove brackets FASMARM not crash end if FASM 1.73.09 work`s fine |
|||
01 Dec 2019, 06:04 |
|
revolution 01 Dec 2019, 09:05
murder wrote: revolution I will fix all these problems as soon as I am able. |
|||
01 Dec 2019, 09:05 |
|
Goto page Previous 1, 2, 3 ... 30, 31, 32, 33 Next < Last Thread | Next Thread > |
Forum Rules:
|
Copyright © 1999-2024, Tomasz Grysztar. Also on GitHub, YouTube.
Website powered by rwasa.