This is just a small thingy:

It is said that ORPS/ANDPS/XORPS/ANDNPS perform corresponding logical operations on the 4 singles of 2 xmm-registers bitwise.
Also, ORPD/ANDPD/XORPD/ANDNPD do the the same logical operations, but on 2 doubles. But since all of these instructions only work on 128bits, each single version is completely equal to its double version, so that both versions can be randomly exchanged or one version can be spared at all.
It even seems that they return the same mxcsr flags and even have the same exception behaviour.

This leads me to the point, that these 4 double precision logical instructions which were introduced with the SSE2 are completely superfluous.(No need to fill the overbloated datasheet with unneccessary further instructions)
Furthermore, those double precision instructions are 1 byte longer.

Anyway, best we can do is ignoring those instructions.

Hy MCD,
single, double are floating point numbers with different precisions...

but if you can use instructions one byte smaller you can optimize 256 byte intros for example.

If they were integers - there would be no difference between 128bit at a time or 1bit at a time.
But like Matrix said - these work on floating point values so there is a precision difference and also if you have double for example then you don't need to first convert it to single because you already have the appropriate functions.

As far as I know, the "or", "and", "andn" and "xor" SSE-instructions simply perform logical operations on each of the 128bits of 2 xmm-registers, there is no floating point calculation stuff. This actually means that mantissa, exponent and sign are all treated the same way, like it is just a big 128bit integer.

I just verified this with OllyDbg v1.1. (On a Pentium 4 machine with "double precision" versions of the instructions worked around with a "db 66h" before those since Olly doesn't SSE2/3).

if ANDPS, ORPS, XORPS and ANDNPS do the same as their respective suffix PD opcodes, then they are redundant.

I first thought maybe they affect SIMD FP execptions but after looking at documentation I found this was not the case.
NaNs don't seem to be a factor with these instructions.

MAYBE the suffix PD instructions are faster than the suffix PS ones.

Well, actually, my TSCBENCW program with those instruction showed for both versions a 1 cycle clock; and actually its unlikely that different binary logical instructions have different timings, cause they are one of the most simplest to add in the ALU.

From Intel manuals, vol. 1, chapter 11.6.9:
... In this example, XORPS or PXOR can be used instead of XORPD and yield the same correct result. However, because of type mismatch between the operand data type and the instruction data type, a latency penalty will be incurred due to implementations of the instructions at the microarchitecture level.

So, two logical instructions XORPS/XORPD, ANDPS/ANDPD are functionally equivalent, but using single precision instruction on double values is slower than doing double calculations with double values. At least, Intel says so.