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FlashBurn



Joined: 06 Jan 2005
Posts: 87
FlashBurn
Quote:

"syscall" and "sysret" are the new instructions (introduced by both AMD64 and Intel EM64T).


Cool, so I haven´t to write these 2 opcodes by myself anymore Smile
Post 19 Feb 2005, 12:23
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MazeGen



Joined: 06 Oct 2003
Posts: 977
Location: Czechoslovakia
MazeGen
I don't want to be tedious, but there are some inconsistencies...
Privalov wrote:
"more strict checking of operands for few instructions" added - "mov ds,eax" is in fact invalid instruction, since such MOV always uses 16-bit size (use "mov ds,ax" instead, there will be no any prefix added).

Intel Instruction Set Reference wrote:

... MOV DS, EAX ...
When the processor executes the instruction with a 32-bit general-purpose register, it assumes that the 16 least-significant bits of the general-purpose register are the destination or source operand.

Privalov wrote:
However "mov eax,ds" is still allowed, because in this exceptional case the all 32 bits of target are affected (the value is zero-extended).

Intel Instruction Set Reference wrote:

... MOV EAX, DS ...
If the register is a destination operand, the resulting value in the two high-order bytes of the register is implementation dependent. For the Pentium 4, Intel Xeon, and P6 family processors, the two high-order bytes are filled with zeros; for earlier 32-bit IA-32 processors, the two high order bytes are undefined.

Wink

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Post 19 Feb 2005, 16:00
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Tomasz Grysztar



Joined: 16 Jun 2003
Posts: 7797
Location: Kraków, Poland
Tomasz Grysztar
Yeah, there are. The AMD has it a bit more clear.
Post 19 Feb 2005, 16:58
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