When assigning values for the GDT table to be able to use 4 gig of memory, you have to use the folowing - xxxxxx: DW FFFFF, 0x0000, ... ,the emphasis is on the 5 F's; that is what tells the chip that you want up to four gig of memory. Now, in 16 bit mode, that is the mode you should be in to do this, FASM, at compile throws up an error, complaining it can not work with FFFFF value. So, how does one get around this problem, any ideas?

Here's some info
How to get into protected mode? First, you need a GLOBAL DESCRIPTOR
TABLE (GDT). There is one at the end of this file, at address "gdt:"
The GDT contains 8-byte DESCRIPTORS for each protected-mode segment.
Each descriptor contains a 32-bit segment base address, a 20-bit segment
limit, and 12 bits describing the segment type. The descriptors look
like this:

MSB bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 LSB
+-------+-------+-------+-------+-------+-------+-------+-------+
byte 0 | bit 7<---------------- segment limit------------------->bit 0 |
+-------+-------+-------+-------+-------+-------+-------+-------+

+-------+-------+-------+-------+-------+-------+-------+-------+
byte 1 |bit 15<---------------- segment limit------------------->bit 8 |
+-------+-------+-------+-------+-------+-------+-------+-------+

+-------+-------+-------+-------+-------+-------+-------+-------+
byte 2 | bit 7<---------------- segment base-------------------->bit 0 |
+-------+-------+-------+-------+-------+-------+-------+-------+

+-------+-------+-------+-------+-------+-------+-------+-------+
byte 3 |bit 15<---------------- segment base-------------------->bit 8 |
+-------+-------+-------+-------+-------+-------+-------+-------+

+-------+-------+-------+-------+-------+-------+-------+-------+
byte 4 |bit 23<---------------- segment base-------------------->bit 16|
+-------+-------+-------+-------+-------+-------+-------+-------+

+-------+-------+-------+-------+-------+-------+-------+-------+
byte 5 | P | DPL | <----------- segment type ----------> |
+-------+-------+-------+-------+-------+-------+-------+-------+

P is the Segment Present bit. It should always be 1.

DPL is the DESCRIPTOR PRIVILEGE LEVEL. For simple code like this, these
two bits should always be zeroes.

Segment Type (again, for simple code like this) is hex 12 for data
segments, hex 1A for code segments.

+-------+-------+-------+-------+-------+-------+-------+-------+
byte 6 | G | B | 0 | avail | bit 19<-- seg limit--->bit 16 |
+-------+-------+-------+-------+-------+-------+-------+-------+

G is the Limit Granularity. If zero, the segment limit is in bytes
(0 to 1M, in 1-byte increments). If one, the segment limit is in 4K PAGES
(0 to 4G, in 4K increments). For simple code, set this bit to 1, and
set the segment limit to its highest value (FFFFF hex). You now have
segments that are 4G in size! The Intel CPUs can address no more than
4G of memory, so this is like having no segments at all. No wonder
protected mode is popular.

B is the Big bit; also called the D (Default) bit. For code segments,
all instructions will use 32-bit operands and addresses by default
(BITS 32, in NASM syntax, USE32 in Microsoft syntax) if this bit is set.
16-bit protected mode is not very interesting, so set this bit to 1.

None of these notes apply to the NULL descriptor. All of its bytes
should be set to zero.

+-------+-------+-------+-------+-------+-------+-------+-------+
byte 7 |bit 31<---------------- segment base------------------->bit 24 |
+-------+-------+-------+-------+-------+-------+-------+-------+

Build a simple GDT with four descriptors: NULL (all zeroes), linear data
(lets you use 32-bit addresses), code, and data/stack. (An extra
descriptor or two is needed to return to real mode.) For simplicity,
the limits of all descriptors (except NULL and the real-mode descriptors)
are FFFFF hex, the largest possible limit.

So you would do some thing like this:

So if you take sys_code_1 as a example.

DEX4U,
According to the geezer code examples,

sys_code_1:
dw 0FFFFh < HERE IS YOUR FIRST 4 F's >>This pertains to the memory designation. If this is FFFFFh, then you access 4 gig.
dw 0
db 0
db 10011010b >>This line and the next line pertain to ring 0, code, data, ..., etc.
db 11001111b < HERE'S YOUR 5th F (the last 4 one's, F in binary ).
db 0
The problem I am having is if make the change to FFFFFh, FASM compile results in an error. With NASM, their is no error. I was just wondering if their is something I am missing with FASM.

But it is in two parts, only the first dw 0ffffh
is here

And here is where the other nible is

DEX4U,
Lets see if I got this straight,

db 1100xxxxb <Here is were the other F goes( were the xxxx are).

If this is where the fifth F goes, 11001111b, this = CFh. So, does C designate page-granular, 32-bit. Any idea what that means?

Is there any special reason not to read the official Intel documentation on protected mode setup and GDT ?