Hi, Matrix.
Well, I belive, on K7 core (athlon) and P6 core (P2 & PIII) mov ebx,imm32 instruction has execute latency of 1.
The same as or mreg32,imm8 (sign extended).
On NetBurst core (PIV) both of them have the latency of 0.5.
The last opcode is 2 bytes shorter, so is preferable in general:

About and [mem],reg and or [mem],reg, I can't say I dont like them
I just try to avoid unnecessary memory access, if calculations can be done via CPU registers - such instructions are usually smaller and faster. I suppose this might be substituted with just chose the right way to calculate the mask.
Btw, write_bitstream routine seems very long, compare it to my code. (however, mine relys on BitStream structure and does related modifications of its fields in addition to yours. This BitStream is what I call HLL style). Though I'm not sure mine is Ok - I can't compile lzss library for some weird reason

don't say this:
Code:

I suppose this might be substituted with
Code:


i was assigning those bits not just setting zeroes,
if bit was 1 that was not supposed to, will be 0
[edi] was a part of a bit string

PS
take into account the fact, we're appending bits, not replacing.

now my shrd shld less function should be all right too, its updated

did you read the first post of Decard?
his code does similar to my.
not just setting bits, but also re-setting them.

Do you mean we're not able to move 0 to whole DWORD at the end of stream, and set some bits to 1 then ?
As I understand 'bitstream', this has serial access, not random.

I don't see the use of BitStream structure in yours.

And while there are free registers i whouldn't use memory for such in a core function. ECX hi part, ebp, esp, esi, es, fs, gs, fs, ss are still freeee

Nope! es, fs, gs, fs, ss are reserved by windows.

thanks for your codes . Now I will implement your solutions in the library and see how they work.