flat assembler
Message board for the users of flat assembler.

Index > Main > Intel Proposes 64-bit Mode-Only Solution (x86S)

Goto page Previous  1, 2
Author
Thread Post new topic Reply to topic
sylware



Joined: 23 Oct 2020
Posts: 422
Location: Marseille/France
sylware 13 Jun 2023, 23:29
... and it seems that the choice of removing the FLAGS from arithmetic ops is a killer feature in out-of-order processors.
Post 13 Jun 2023, 23:29
View user's profile Send private message Reply with quote
sylware



Joined: 23 Oct 2020
Posts: 422
Location: Marseille/France
sylware 20 Aug 2023, 18:32
Yep, the specs of "RISC-V for x86_64" and more were released Smile

More conditional instructions (no branch) and what seems better data movment among avx regs.

Maybe we should go full conditional instructions like in GPUs, not only "thread" based but also flags based, that to keep real branches only when it is *really* required.
Post 20 Aug 2023, 18:32
View user's profile Send private message Reply with quote
Furs



Joined: 04 Mar 2016
Posts: 2453
Furs 21 Aug 2023, 12:26
sylware wrote:
Yep, the specs of "RISC-V for x86_64" and more were released Smile

More conditional instructions (no branch) and what seems better data movment among avx regs.

Maybe we should go full conditional instructions like in GPUs, not only "thread" based but also flags based, that to keep real branches only when it is *really* required.
Funny, didn't ARM go the other way around when going from 32-bit to 64-bit? Get rid of conditionals?
Post 21 Aug 2023, 12:26
View user's profile Send private message Reply with quote
sylware



Joined: 23 Oct 2020
Posts: 422
Location: Marseille/France
sylware 21 Aug 2023, 12:58
@Furs

Well, I am not a high performance GPU designer, so I would not be suprised if conditional were significantly hurting performance.
What I heard: the flags tied to many arithmetic operations are hurting performance in out-of-order CPUs. This would be one of the reasons you did not have that is RISC-V.
arm did get rid of them is a strong signal to favor conditionals are actually hurting performance, but intel adding more is also a strong signal.

In the end, RISC-V should observe, test and benchmark (in R&D), but must be ready to add a bunch of them if it is has a significant performance impact, and I really mean "significant".
Post 21 Aug 2023, 12:58
View user's profile Send private message Reply with quote
revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 20142
Location: In your JS exploiting you and your system
revolution 21 Aug 2023, 13:21
Furs wrote:
Funny, didn't ARM go the other way around when going from 32-bit to 64-bit? Get rid of conditionals?
It still has some, but much fewer.

I'm not convinced it was for performance though. At least not directly. I believe it was mostly to free up bits to address the extra 16 registers. So the doubling of register space may have given some performance improvements for some workloads, and the loss of abundant conditionals hurt less than the gains for a large proportion of running code.

Plus the problem of many HLLs with making good use (or indeed any use) of the conditions. The HLLs always seemed to struggle to know how to use them well. So I guess ARM decided that they were rarely used, thus no sense keeping them. Question
sylware wrote:
In the end, RISC-V should observe, test and benchmark (in R&D), but must be ready to add a bunch of them if it is has a significant performance impact, and I really mean "significant".
Do you mean to suggest that RISC-V might add a flag register later? If so then I highly doubt it. It appears to be a core tenet of the design.
Post 21 Aug 2023, 13:21
View user's profile Send private message Visit poster's website Reply with quote
sylware



Joined: 23 Oct 2020
Posts: 422
Location: Marseille/France
sylware 21 Aug 2023, 13:40
@revolution

Kind of true. I guess conditionals on RISC-V would target a general register used as "read only flags".

I think in the new 64bits-only intel, there is a way to disable the update of the flags now (could not really find it though, I just did skim thru the document).

That said, RISC-V has a GPU side in the works where "vector instructions" are conditionals on a "thread" mask (like AMD GPU isa, and I guess nvidia GPU isa).

And conditionals, from a RISC perspective are just a few instructions with one branch probably not going in the "big bad predictor". Actually, that would be a way to do that: branch instructions which were "super local". But if arms removed them, they probably would not be worth it: instructions fusing could do all that for instance.

Yep, better be super extra careful about those conditionals.
Post 21 Aug 2023, 13:40
View user's profile Send private message Reply with quote
Display posts from previous:
Post new topic Reply to topic

Jump to:  
Goto page Previous  1, 2

< Last Thread | Next Thread >
Forum Rules:
You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot vote in polls in this forum
You cannot attach files in this forum
You can download files in this forum


Copyright © 1999-2024, Tomasz Grysztar. Also on GitHub, YouTube.

Website powered by rwasa.