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Index > Main > I dont remember how to denote 128 bit memory locations

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Zoltanmatey31



Joined: 10 Jan 2023
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Zoltanmatey31 20 Jan 2023, 19:39
"the second one can be also a SSE register or 128–bit memory location."

Also perhaps Fsave (now i am not sure) there was an instruction to store fpu registers and xmm registers even i think, and it would require 512 bits memory location. How to denote that on a label?
Post 20 Jan 2023, 19:39
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Tomasz Grysztar



Joined: 16 Jun 2003
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Tomasz Grysztar 20 Jan 2023, 19:52
There is a table in the manual that lists all the size operators.
Post 20 Jan 2023, 19:52
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Zoltanmatey31



Joined: 10 Jan 2023
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Zoltanmatey31 20 Jan 2023, 20:17
Tomasz Grysztar wrote:
There is a table in the manual that lists all the size operators.


Thanks! Although it wasn't in the pdf coming with the windows package (i definitely cant remember 512 bites long datatype).
Post 20 Jan 2023, 20:17
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Zoltanmatey31



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Zoltanmatey31 20 Jan 2023, 20:20
ok i just skipped that part.
Post 20 Jan 2023, 20:20
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Zoltanmatey31



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Zoltanmatey31 23 Jan 2023, 14:12
Tomasz Grysztar wrote:
There is a table in the manual that lists all the size operators.


So i write that i have skipped that part. But i actually read below another table with db, dw, dd, etc.

which did not contain all the size definition operator.
After your post i thought that this is a feature of fasm and it very well fits fasm this way not being a nasm styled for example (whatever way nasm is actually styled in)

so then i would have to define macros or labels or so for those size operators if i want a shorter form (so then some lables maybe dz or something or not so if i define it as a size operator).

Is that so?
Post 23 Jan 2023, 14:12
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DimonSoft



Joined: 03 Mar 2010
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DimonSoft 24 Jan 2023, 14:17
If I understand the question the right way (“why are there no dX directives for 128+ bits?”), the answer seems to be quite easy: SSE and stuff, although they use large 128/256/512 bit registers don’t store single 128/256/512 bit values there: each such register is considered to be a set of 4/8/other number of 2/4/8 bytes-sized values, so there’s no need to provide new data definition directives that would be of no use anyway. (And, AFAIR, FASM uses 65 bits for its internal numeric values representation, so that might be another, but definitely not the main, reason.)
Post 24 Jan 2023, 14:17
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
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revolution 25 Jan 2023, 06:19
Where could you load 128 bit data to?

If we extend the GPRs to 128 bits, and also assume that the naming follows the qwerty pattern, then we get a new set of registers TAX, TDX, TCX, ..., T15.
Code:
all_my_money do $21 ; octal word, oword. do == define owords. Like dw == define words
mov tax,[all_my_money] ; pay the IRD 21 dollars Razz    
Post 25 Jan 2023, 06:19
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Roman



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Roman 25 Jan 2023, 11:07
Quote:
TAX, TDX, TCX, ..., T15.

In 128bits cup must be 32 registers !
Post 25 Jan 2023, 11:07
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
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revolution 25 Jan 2023, 18:16
Roman wrote:
In 128bits cup must be 32 registers !
Okay. Then we need to add a TEX prefix.

Now I wished the naming used S instead of T.
Post 25 Jan 2023, 18:16
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Zoltanmatey31



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Zoltanmatey31 25 Jan 2023, 19:53
but fsave or something like this which saves various data of fpu or otherwise stores varried data. not simply repeats of 8 16 or 32 bits (or 64)
Post 25 Jan 2023, 19:53
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